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38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 1 description the 38b7 group is the 8-bit microcomputer based on the 740 family core technology. the 38b7 group has six 8-bit timers, one 16-bit timer, a fluorescent display automatic display circuit, 16-channel 10-bit a-d converter, a serial i/o with automatic transfer function, which are available for controlling musical instruments and household appliances. the 38b7 group has variations of internal memory type. for details, refer to the section on part numbering. for details on availability of microcomputers in the 38b7 group, refer to the section on group expansion. built-in pull-down resistors connected to high-breakdown voltage ports are available by specifying with the mask option in the mask rom version. for the details, refer to the section on the mask option of pull-down resistor. features basic machine-language instructions ....................................... 71 the minimum instruction execution time .......................... 0.48 s (at 4.19 mhz oscillation frequency) memory size rom ........................................................ 60k bytes ram .......................................................2048 bytes programmable input/output ports ............................................. 75 high-breakdown-voltage output ports ...................................... 52 software pull-up resistors . (ports p6 4 to p6 7 , p7, p8 0 to p8 3 , p9, pa, pb) interrupts .................................................. 22 sources, 16 vectors timers ........................................................... 8-bit ? 6, 16-bit ? 1 serial i/o1 (clock-synchronized) ................................... 8-bit ? 1 (max. 256-byte automatic transfer function) serial i/o2 (uart or clock-synchronized) .................... 8-bit ? 1 serial i/o3 (clock-synchronized) ................................... 8-bit ? 1 pwm ............................................................................ 14-bit ? 1 8-bit ? 1 (also functions as timer 6) a-d converter .............................................. 10-bit ? 16 channels d-a converter ................................................................ 1 channel fluorescent display function ......................... total 56 control pins interrupt interval determination function ..................................... 1 (serviceable even in low-speed mode) watchdog timer ............................................................ 16-bit ? 1 buzzer output ............................................................................. 1 two clock generating circuits main clock (x in ? out ) .......................... internal feedback resistor sub-clock (x cin ? cout ) .......... without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) power source voltage in high-speed mode ................................................... 4.0 to 5.5 v (at 4.19 mhz oscillation frequency and high-speed selected) in middle-speed mode ........................................... 2.7 to 5.5 v (*) (at 4.19 mhz oscillation frequency and middle-speed selected) in low-speed mode ................................................ 2.7 to 5.5 v (*) (at 32 khz oscillation frequency) (*: 4.0 to 5.5 v for flash memory version) power dissipation in high-speed mode .......................................................... 35 mw (at 4.19 mhz oscillation frequency) in low-speed mode ............................................................. 60 w (at 32 khz oscillation frequency, at 3 v power source voltage) operating temperature range ................................... ?0 to 85 ? supply voltage ................................................. v cc = 5 v ?10 % program/erase voltage ............................... v pp = 11.7 to 12.6 v programming method ...................... programming in unit of byte erasing method batch erasing ........................................ parallel/serial i/o mode block erasing .................................... cpu reprogramming mode program/erase control by software command number of times for programming/erasing ............................ 100 operating temperature range (at programming/erasing) ..................................................................... normal temperature notes 1. the flash memory version cannot be used for application em- bedded in the mcu card. 2. power source voltage vcc of the flash memory version is 4.0 to 5.5 v. application musical instruments, vcr, household appliances, etc.
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 2 fig. 1 pin configuration of M38B79mfh-xxxxfp pin configuration (top view) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 0 0 m 3 8 b 7 9 m f h - x x x x f p * p 4 7 / f l d 3 9 * p 0 0 / f l d 8 * p 0 3 / f l d 1 1 * p 0 4 / f l d 1 2 * p 0 5 / f l d 1 3 * p 0 6 / f l d 1 4 * p 0 7 / f l d 1 5 * p 1 1 / f l d 1 7 * p 1 2 / f l d 1 8 * p 1 3 / f l d 1 9 * p 1 4 / f l d 2 0 * p 1 5 / f l d 2 1 * p 1 6 / f l d 2 2 * p 1 7 / f l d 2 3 * p 1 0 / f l d 1 6 * p 0 1 / f l d 9 * p 0 2 / f l d 1 0 v e e * p 4 6 / f l d 3 8 * p 4 3 / f l d 3 5 * p 4 2 / f l d 3 4 * p 4 1 / f l d 3 3 * p 4 0 / f l d 3 2 * p 3 7 / f l d 3 1 * p 3 6 / f l d 3 0 * p 3 5 / f l d 2 9 * p 3 4 / f l d 2 8 * p 3 3 / f l d 2 7 * p 3 2 / f l d 2 6 * p 3 1 / f l d 2 5 * p 3 0 / f l d 2 4 * p 4 5 / f l d 3 7 * p 4 4 / f l d 3 6 p b 5 / s o u t 1 p b 4 / s c l k 1 1 p b 3 / s s t b 1 p a 6 / a n 6 p a 7 / a n 7 v r e f a v s s p 9 0 / s i n 3 / a n 8 p 9 1 / s o u t 3 / a n 9 p 9 2 / s c l k 3 / a n 1 0 p 9 4 / r t p 1 / a n 1 2 p 9 5 / r t p 0 / a n 1 3 p 9 6 / p w m 0 / a n 1 4 p 9 7 / b u z 0 2 / a n 1 5 p b 2 / s b u s y 1 p a 1 / a n 1 p a 0 / a n 0 p 8 1 / x c o u t p 8 0 / x c i n p 7 4 / p w m 1 p 7 3 / i n t 3 / d i m o u t p 7 2 / i n t 2 p 7 1 / i n t 1 p 7 0 / i n t 0 p a 5 / a n 5 p b 0 / s c l k 1 2 / d a p b 1 / s r d y 1 p 7 5 / t 1 o u t x i n x o u t v c c p 7 6 / t 3 o u t v s s p 7 7 / i n t 4 / b u z 0 1 r e s e t p a 4 / a n 4 p a 3 / a n 3 p a 2 / a n 2 * p 2 0 / f l d 0 * p 2 1 / f l d 1 * p 2 2 / f l d 2 * p 2 3 / f l d 3 * p 2 4 / f l d 4 * p 2 5 / f l d 5 * p 2 6 / f l d 6 * p 2 7 / f l d 7 p b 6 / s i n 1 * p 5 1 / f l d 4 1 * p 5 0 / f l d 4 0 * p 5 3 / f l d 4 3 * p 5 2 / f l d 4 2 * p 5 5 / f l d 4 5 * p 5 4 / f l d 4 4 * p 5 7 / f l d 4 7 * p 5 6 / f l d 4 6 * p 6 1 / f l d 4 9 * p 6 0 / f l d 4 8 * p 6 3 / f l d 5 1 * p 6 2 / f l d 5 0 p 6 5 / t x d / f l d 5 3 p 6 4 / r x d / f l d 5 2 p 6 7 / s r d y 2 / s c l k 2 2 / f l d 5 5 p 6 6 / s c l k 2 1 / f l d 5 4 p 8 2 / c n t r 1 c n v s s p 8 3 / c n t r 0 / c n t r 2 p 9 3 / s r d y 3 / a n 1 1 p a c k a g e t y p e : 1 0 0 p 6 s - a * h i g h - b r e a k d o w n - v o l t a g e o u t p u t p o r t : t o t a l i n g 5 2
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 3 fig. 2 functional block diagram functional block diagram p o r t p 0 (8 ) 8 p o r t p 1 ( 8 ) 8 p o r t p 2 ( 8 ) 8 p o r t p 3 ( 8 ) 8 p o r t p 4 ( 8 ) 8 p o r t p 6 ( 8 ) 8 p o r t p 7 ( 8 ) 8 p o r t p 8 ( 4 ) 4 p o r t p 9 ( 8 ) 8 p o r t p a ( 8 ) 8 s y s t e m c l o c k g e n e r a t i o n x i n - x o u t ( m a i n - c l o c k ) x c i n - x c o u t ( s u b - c l o c k ) t i m e r s t i m e r x ( 1 6 - b i t ) t i m e r 1 ( 8 - b i t ) t i m e r 2 ( 8 - b i t ) t i m e r 3 ( 8 - b i t ) t i m e r 4 ( 8 - b i t ) t i m e r 5 ( 8 - b i t ) t i m e r 6 ( 8 - b i t ) a - d c o n v e r t e r ( 1 0 - b i t ? 1 2 c h a n n e l ) c p u c o r e w a t c h d o g t i m e r r o m r a m b u i l d - i n p e r i p h e r a l f u n c t i o n s m e m o r y i / o p o r t s p w m 0 ( 1 4 - b i t ) p w m 1 ( 8 - b i t ) s e r i a l i / o s s e r i a l i / o 1 ( c l o c k - s y n c h r o n i z e d ) ( 2 5 6 b y t e a u t o m a t i c t r a n s f e r ) s e r i a l i / o 2 ( c l o c k - s y n c h r o n i z e d o r u a r t ) f l d d i s p l a y f u n c t i o n 5 6 c o n t r o l p i n s ( 5 2 h i g h - b r e a k d o w n v o l t a g e p o r t s ) i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n f u n c t i o n b u z z e r o u t p u t p o r t p 5 ( 8 ) 8 s e r i a l i / o 3 ( c l o c k - s y n c h r o n i z e d ) p o r t p b ( 7 ) 7
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 4 table 1 pin description (1) pin name function v cc , v ss power source apply voltage of 4.0 5.5 v to v cc , and 0 v to v ss . cnv ss cnv ss connect to v ss . vpp power input pin in flash memory mode. v ee pull-down apply voltage supplied to pull-down resistors of ports p0, p1, p2 and p3. power source v ref reference voltage reference voltage input pin for a-d converter. av ss analog power analog power source input pin for a-d converter. source connect to v ss . ______ reset reset input reset input pin for active l . x in clock input input and output pins for the main clock generating circuit. feedback resistor is built in between x in pin and x out pin. connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the x out clock output oscillation frequency. when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. the clock is used as the oscillating source of system clock. p0 0 /fld 8 output port p0 8-bit output port. fld automatic display p0 7 /fld 15 high-breakdown-voltage p-channel open-drain output structure. pins a pull-down resistor is built in between port p0 and the v ee pin. at reset, this port is set to v ee level. p1 0 /fld 16 i/o port p1 8-bit i/o port. fld automatic display p1 7 /fld 23 i/o direction register allows each pin to be individually programmed as either pins input or output. at reset, this port is set to input mode. low-voltage input level. high-breakdown-voltage p-channel open-drain output structure. a pull-down resistor is built in between port p1 and the v ee pin. at reset, this port is set to v ee level. p2 0 /fld 0 output port p2 8-bit output port with the same function as port p0. fld automatic display p2 7 /fld 7 high-breakdown-voltage p-channel open-drain output structure. pins a pull-down resistor is built in between port p2 and the v ee pin. at reset, this port is set to v ee level. p3 0 /fld 24 i/o port p3 8-bit i/o port with the same function as port p1. fld automatic display p3 7 /fld 31 low-voltage input level. pins high-breakdown-voltage p-channel open-drain output structure. a pull-down resistor is built in between port p3 and the v ee pin. at reset, this port is set to v ee level. p4 0 /fld 32 i/o port p4 8-bit i/o port with the same function as port p1. fld automatic display p4 7 /fld 39 low-voltage input level. pins high-breakdown-voltage p-channel open-drain output structure. a pull-down resistor is not built in between port p4 and the v ee pin. p5 0 /fld 40 i/o port p5 8-bit i/o port with the same function as port p1. fld automatic display p5 7 /fld 47 low-voltage input level. pins high-breakdown-voltage p-channel open-drain output structure. a pull-down resistor is not built in between port p5 and the v ee pin. p6 0 /fld 48 i/o port p6 4-bit i/o port with the same function as port p1. fld automatic display p6 3 /fld 51 low-voltage input level. pins high-breakdown-voltage p-channel open-drain output structure. a pull-down resistor is not built in between port p6 and the v ee pin. function except a port function
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 5 table 2 pin description (2) function except a port function pin name function p6 4 /r x d/fld 52 , i/o port p6 4-bit i/o port . fld automatic display p6 5 /t x d/fld 53 , low-voltage input level for input ports. pins p6 6 /s clk21 /fld 54 , cmos compatible input level for rxd, s clk21 , s clk22 . serial i/o2 function pins p6 7 /s rdy2 /s clk22 / cmos 3-state output structure. fld 55 , p7 0 /int 0 , i/o port p7 8-bit i/o port. interrupt input pins p7 1 /int 1 , cmos compatible input level. p7 2 /int 2 , cmos 3-state output structure. p7 3 /int 3 /dim out , interrupt input pin dimmer signal output pin p7 4 /pwm 1 pwm output pin p7 5 /t1 out , timer output pins p7 6 /t3 out , p7 7 /int 4 /b uz01 interrupt input pin buzzer output pin p8 0 /x cin , i/o port p8 4-bit i/o port with the same function as port p7. i/o pins for sub-clock generating p8 1 /x cout cmos compatible input level. circuit (connect a ceramic resonator cmos 3-state output structure. or a quarts-crystal oscillator) p8 2 /cntr 1 , timer input pin p8 3 /cntr 0 /cntr 2 timer i/o pin p9 0 /s in3 /an 8 , i /o port p9 8-bit i/o port with the same function as port p7. serial i/o3 function pins p9 1 /s out3 /an 9 , cmos compatible input level. a-d converter input pins p9 2 /s clk3 /an 10 , cmos 3-state output structure. p9 3 /s rdy3 /an 11 , p9 4 /rtp 1 /an 12 , real time port output pins p9 5 /rtp 0 /an 13 a-d converter input pins p9 6 /pwm 0 /an 14 14-bit pwm output pin a-d converter input pin p9 7 /b uz02 /an 15 buzzer output pin a-d converter input pin pa 0 /an 0 pa 7 /an 7 i /o port pa 8-bit i/o port with the same function as port p7. a-d converter input pin cmos compatible input level. cmos 3-state output structure. pb 0 /s clk12 /da i /o port pb 7-bit i/o port with the same function as port p7. serial i/o1 function pin cmos compatible input level. d-a converter output pin cmos 3-state output structure. pb 1 /s rdy1 , serial i/o1 function pins pb 2 /s busy1 , pb 3 /s stb1 , pb 4 /s clk11 , pb 5 /s out1 , pb 6 /s in1
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 6 fig. 3 part numbering m 3 8 b 7 9 m f h - x x x x f p p r o d u c t p a c k a g e t y p e f p : 1 0 0 p 6 s - a p a c k a g e r o m n u m b e r o m i t t e d i n f l a s h m e m o r y v e r s i o n r o m / f l a s h m e m o r y s i z e 1 2 3 4 5 6 7 8 9 a b c d e f : 4 0 9 6 b y t e s : 8 1 9 2 b y t e s : 1 2 2 8 8 b y t e s : 1 6 3 8 4 b y t e s : 2 0 4 8 0 b y t e s : 2 4 5 7 6 b y t e s : 2 8 6 7 2 b y t e s : 3 2 7 6 8 b y t e s : 3 6 8 6 4 b y t e s : 4 0 9 6 0 b y t e s : 4 5 0 5 6 b y t e s : 4 9 1 5 2 b y t e s : 5 3 2 4 8 b y t e s : 5 7 3 4 4 b y t e s : 6 1 4 4 0 b y t e s t h e f i r s t 1 2 8 b y t e s a n d t h e l a s t 2 b y t e s o f r o m a r e r e s e r v e d a r e a s ; t h e y c a n n o t b e u s e d f o r u s e r s . m e m o r y t y p e m f : m a s k r o m v e r s i o n : f l a s h m e m o r y v e r s i o n r a m s i z e 0 1 2 3 4 5 6 7 8 9 : 1 9 2 b y t e s : 2 5 6 b y t e s : 3 8 4 b y t e s : 5 1 2 b y t e s : 6 4 0 b y t e s : 7 6 8 b y t e s : 8 9 6 b y t e s : 1 0 2 4 b y t e s : 1 5 3 6 b y t e s : 2 0 4 8 b y t e s h i g h - b r e a k d o w n v o l t a g e p u l l - d o w n o p t i o n r e g a r d i n g o p t i o n c o n t e n t s , r e f e r t o s e c t i o n m a s k o p t i o n o f p u l l - d o w n r e s i s t o r . f o r f l a s h m e m o r y v e r s i o n , t h e r e i s n o t t h e o p t i o n s p e c i f i c a t i o n .
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 7 group expansion mitsubishi plans to expand the 38b7 group as follows. memory type support for mask rom and flash memory versions. memory size flash memory size ........................................................... 60k bytes mask rom size ................................................................ 60k bytes ram size .........................................................................2048 bytes package 100p6s-a .................................. 0.65 mm-pitch plastic molded qfp fig. 4 memory expansion plan currently supported products are listed below. table 3 list of supported products note : products under development: the development schedule and specifications may be revised without notice. as of mar. 2000 product M38B79mfh-xxxxfp M38B79fffp rom size (bytes) rom size for user ( ) 61440 (61310) ram size (bytes) 2048 package 100p6s-a remarks mask rom version flash memory version 6 0 k 5 6 k 5 2 k 4 8 k 4 4 k 3 6 k 3 2 k 2 8 k 2 4 k 2 0 k 1 6 k 1 2 k 8 k 4 k 4 0 k r o m s i z e ( b y t e s ) 2 5 65 1 27 6 8 1 , 0 2 4 1 , 5 3 62 , 0 4 8 r a m s i z e ( b y t e s ) u n d e r d e v e l o p m e n t m 3 8 b 7 9 m f h m 3 8 b 7 9 f f u n d e r d e v e l o p m e n t
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 8 functional description central processing unit (cpu) the 38b7 group uses the standard 740 family instruction set. re- fer to the table of 740 series addressing modes and machine instructions or the 740 series software manual for details on the instruction set. machine-resident 740 series instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 6. store registers other than those described in figure 6 with pro- gram when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 5 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 9 table 4 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 6 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p re t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) e x e c u t e r t i ( p s )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 i n t e r r u p t s e r v i c e r o u t i n e p o p c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) ( s ) ( s ) 1 ( p c l )m ( s ) ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) p o p r e t u r n a d d r e s s f r o m s t a c k i f l a g i s s e t f r o m 0 t o 1 f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) i n t e r r u p t d i s a b l e f l a g i s 0
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 10 [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . bit 5: index x mode flag (t) when the t flag is 0 , arithmetic operations are performed between accumulator and memory. when the t flag is 1 , direct arithmetic operations and direct data transfers are enabled between memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 5 set and clear instructions of each bit of processor status register set instruction clear instruction c flag z flag i flag d flag b flag t flag v flag n flag sec clc _ _ sei cli sed cld _ _ set clt clv _ _ _
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 11 [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the internal system clock selection bit etc. the cpu mode register is allocated at address 003b 16 . fig. 7 structure of cpu mode register c p u m o d e r e g i s t e r ( c p u m : a d d r e s s 0 0 3 b 1 6 ) b 7 b 0 p r o c e s s o r m o d e b i t s b 1 b 0 0 0 : s i n g l e - c h i p m o d e 0 1 : 1 0 : n o t a v a i l a b l e 1 1 : p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n 1 : x c i n x c o u t o s c i l l a t i n g f u n c t i o n m a i n c l o c k ( x i n x o u t ) s t o p b i t 0 : o s c i l l a t i n g 1 : s t o p p e d m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t 0 : f ( x i n ) ( h i g h - s p e e d m o d e ) 1 : f ( x i n ) / 4 ( m i d d l e - s p e e d m o d e ) i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t 0 : x i n - x o u t s e l e c t i o n ( m i d d l e - / h i g h - s p e e d m o d e ) 1 : x c i n - x c o u t s e l e c t i o n ( l o w - s p e e d m o d e ) s t a c k p a g e s e l e c t i o n b i t 0 : p a g e 0 1 : p a g e 1 n o t u s e d ( r e t u r n 1 w h e n r e a d ) ( d o n o t w r i t e 0 t o t h i s b i t . )
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 12 memory special function register (sfr) area the special function register (sfr) area contains control registers for i/o ports, timers and other functions. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing, and the other areas are user areas for storing pro- grams. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the special page addressing mode can be used to specify memory addresses in the special page area. access to this area with only 2 bytes is possible in the special page addressing mode. fig. 8 memory map diagram 0100 16 0000 16 0040 16 0440 16 ff00 16 ffdc 16 fffe 16 ffff 16 192 256 384 512 640 768 896 1024 1536 2048 xxxx 16 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 yyyy 16 zzzz 16 ram rom 0ee0 16 0f00 16 0eff 16 0fff 16 0edf 16 0e00 16 reserved area sfr area 1 not used (note) interrupt vector area rom area reserved rom area (common rom area,128 bytes) zero page special page ram area ram size (byte) address xxxx 16 rom size (byte) address yyyy 16 reserved rom area address zzzz 16 sfr area 2 ram area for serial i/o automatic transfer note : when 1024 bytes or more are used as ram area, this area can be used. ram area for fld automatic display
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 13 fig. 9 memory map of special function register (sfr) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 serial i/o2 transmit/receive buffer register (tb/rb) port p0 (p0) port p1 (p1) port p2 (p2) port p3 direction register (p3d) port p3 (p3) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) port p8 (p8) port p8 direction register (p8d) serial i/o1 automatic transfer data pointer (sio1dp) serial i/o1 control register 1 (sio1con1) serial i/o1 control register 2 (sio1con2) serial i/o1 register/transfer counter (sio1) serial i/o1 control register 3 (sio1con3) serial i/o2 control register (sio2con) serial i/o2 status register (sio2sts) port p9 (p9) port p9 direction register (p9d) 0ef0 16 0ef1 16 0ef2 16 0ef3 16 0ef4 16 0ef5 16 0ef6 16 0ef7 16 toff2 time set register (toff2) pull-up control register 1 (pull1) pull-up control register 2 (pull2) fldc mode register (fldm) tdisp time set register (tdisp) toff1 time set register (toff1) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 timer x mode register 1 (txm1) interrupt control register 2(icon2) timer 1 (t1) timer 2 (t2) timer 3 (t3) timer 4 (t4) timer 5 (t5) timer 6 (t6) pwm control register (pwmcon) timer 6 pwm register (t6pwm) timer 12 mode register (t12m) timer 34 mode register (t34m) timer 56 mode register (t56m) timer x (low-order) (txl) timer x (high-order) (txh) timer x mode register 2 (txm2) interrupt interval determination register (iid) interrupt interval determination control register (iidcon) ad/da control register (adcon) a-d conversion register (low-order) (adl) a-d conversion register (high-order) (adh) interrupt source switch register (ifr) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1(ireq1) interrupt request register 2(ireq2) interrupt control register 1(icon1) 0ef8 16 0ef9 16 0efa 16 0efb 16 0efc 16 0efd 16 0efe 16 0eff 16 fld data pointer (flddp) port p4 fld/port switch register (p4fpr) port p5 fld/port switch register (p5fpr) port p6 fld/port switch register (p6fpr) fld output control register (fldcon) buzzer output control register (buzcon) port p1 direction register (p1d) pwm register (high-order) (pwmh) pwm register (low-order) (pwml) baud rate generator (brg) uart control register (uartcon) port pa (pa) port pa direction register (pad) port pb (pb) port pb direction register (pbd) 0eec 16 0eed 16 serial i/o3 control register (sio3con) serial i/o3 register (sio3) 0eee 16 watchdog timer control register (wdtcon) 0eef 16 pull-up control register 3 (pull3) port p0 digit output set switch register (p0dor) port p2 digit output set switch register (p2dor) flash memory control register (fcon) flash command register (fcmd) (note) (note) note: flash memory version only. d-a conversion register (da)
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 14 i/o ports [direction registers] pid the 38b7 group has 75 programmable i/o pins arranged in ten in- dividual i/o ports (p1, p3, p4, p5, p6, p7, p8, p9, pa and pb). the i/o ports have direction registers which determine the input/ output direction of each individual pin. each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin becomes an input pin. when 1 is written to that pin, that pin becomes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input (the bit corresponding to that pin must be set to 0 ) are floating and the value of that pin can be read. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. fig. 10 structure of pull-up control registers (pull1, pull2 and pull3) [high-breakdown-voltage output ports] the 38b7 group has seven ports with high-breakdown-voltage pins (ports p0 to p5 and p6 0 p6 3 ). the high-breakdown-voltage ports have p-channel open-drain output with vcc 45 v of break- down voltage. each pin in ports p0 to p3 has an internal pull-down resistor connected to v ee . at reset, the p-channel output transis- tor of each port latch is turned off, so that it goes to v ee level ( l ) by the pull-down resistor. writing 1 (weak drivability) to bit 7 of the fldc mode register (address 0ef4 16 ) shows the rising transition of the output transis- tors for reducing transient noise. at reset, bit 7 of the fldc mode register is set to 0 (strong drivability). [pull-up control register] pull ports p6 4 p6 7 , p7, p8 0 p8 3 , p9, pa and pb have built-in pro- grammable pull-up resistors. the pull-up resistors are valid only in the case that the each control bit is set to 1 and the correspond- ing port direction registers are set to input mode. 0: no pull-up 1: pull-up pull-up control register 3 (pull3 : address 0eef 16 ) pa 0 , pa 1 pull-up control bit pa 2 , pa 3 pull-up control bit pa 4 , pa 5 pull-up control bit pa 6 , pa 7 pull-up control bit pb 0 , pb 1 pull-up control bit pb 2 , pb 3 pull-up control bit pb 4 , pb 5 pull-up control bit pb 6 pull-up control bit b7 b0 0: no pull-up 1: pull-up pull-up control register 1 (pull1 : address 0ef0 16 ) p6 4 , p6 5 pull-up control bit p6 6 , p6 7 pull-up control bit p7 0 , p7 1 pull-up control bit p7 2 , p7 3 pull-up control bit p7 4 , p7 5 pull-up control bit p7 6 , p7 7 pull-up control bit not used (returns 0 when read) (do not write 1 .) b7 b0 pull-up control register 2 (pull2 : address 0ef1 16 ) p8 0 , p8 1 pull-up control bit p8 2 , p8 3 pull-up control bit p9 0 , p9 1 pull-up control bit p9 2 , p9 3 pull-up control bit p9 4 , p9 5 pull-up control bit p9 6 , p9 7 pull-up control bit not used (returns 0 when read) (do not write 1 .) b7 b0 not used (returns 0 when read) (do not write 1 .) 0: no pull-up 1: pull-up
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 15 table 6 list of i/o port functions (1) pin p0 0 /fld 8 p0 7 /fld 15 nama port p0 input/output output i/o format high-breakdown voltage p-channel open-drain output with pull-down resistor low-voltage input level high-breakdown voltage p-channel open-drain output with pull-down resistor high-breakdown voltage p-channel open-drain output with pull-down resistor low-voltage input level high-breakdown voltage p-channel open-drain output with pull-down resistor low-voltage input level high-breakdown voltage p-channel open-drain output low-voltage input level high-breakdown voltage p-channel open-drain output low-voltage input level high-breakdown voltage p-channel open-drain output low-voltage input level (port input) cmos compatible input level (rxd, s clk21 , s clk22 ) cmos 3-state output non-port function fld automatic display function related sfrs fldc mode register p0 digit output set switch register ref.no. (1) (2) fldc mode register fld automatic display function serial i/o2 function i/o p1 0/ fld 16 p1 7 /fld 23 port p1 input/output, individual bits fldc mode register p2 digit output set switch register (1) p2 0 /fld 0 p2 7 /fld 7 port p2 output p3 0 /fld 24 p3 7 /fld 31 port p3 input/output, individual bits fldc mode register (2) fldc mode register port p4 fld/port switch register (2) p4 0 /fld 32 p4 7 /fld 39 port p4 input/output, individual bits input/output, individual bits p5 0 /fld 40 p5 7 /fld 47 port p5 fldc mode register port p5 fld/port switch register (2) fldc mode register port p6 fld/port switch register (2) input/output, individual bits port p6 p6 0 /fld 48 p6 3 /fld 51 p6 4 /rxd/ fld 52 p6 5 /txd/ fld 53 , p6 6 /s clk21 / fld 54 p6 7 /s rdy2 / s clk22 / fld 55 p7 0 /int 0 , p7 1 /int 1 p7 2 /int 2 cmos compatible input level cmos 3-state output fldc mode register serial i/o2 control register uart control register interrupt edge selection register (3) (4) (5) (6) port p7 input/output, individual bits external interrput input interrupt edge selection register interrupt interval determi- nation control register interrupt edge selection register fld output control register timer 56 mode register timer 12 mode register timer 34 mode register buzzer output control register interrupt edge selection register cpu mode register (7) p7 3 /int 3 / dim out external interrput input dimmer signal output (8) p7 4 /pwm 1 p7 5 /t1 out p7 6 /t3 out p7 7 /int 4 / b uz01 cmos compatible input level cmos 3-state output pwm output timer output timer output buzzer output external interrput input (9) sub-clock generating circuit i/o external count input p8 0 /x cin p8 1 /x cout p8 2 /cntr 1 p8 3 /cntr 0 / cntr 2 port p8 input/output, individual bits (10) (11) (6) (12) interrupt edge selection register
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 16 notes 1 : how to use double-function ports as function i/o ports, refer to the applicable sections. 2 : make sure that the input level at each pin is either 0 v or vcc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from vcc to vss through the input-stage gate. table 7 list of i/o port functions (2) pin p9 0 /s in3 / an 8 p9 1 /s out3 / an 9 , p9 2 /s clk3 / an 10 p9 3 /s rdy3 / an 11 p9 4 /rtp 1 / an 12 , p9 5 /rtp 0 / an 13 p9 6 /pwm 0 / an 14 p9 7 /b uz02 / an 15 pa 0 /an 0 pa 7 /an 7 nama port p9 input/output input/output, individual bits non-port function serial i/o3 function i/o a-d conversion input related sfrs serial i/o3 control register ad/da control register ref.no. (6) i/o format cmos compatible input level cmos 3-state output port pa cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output (13) (14) (15) real time port output a-d conversion input timer x mode register 2 ad/da control register pwm output a-d conversion input buzzer output a-d conversion input a-d conversion input pwm control register ad/da control register buzzer output control register ad/da control register ad/da control register (16) (16) (17) pb 0 /s clk12 / da pb 1 /s rdy1 pb 2 /s busy1 pb 3 /s stb1 pb 4 /s clk11 pb 5 /s out1 pb 6 /s in1 (18) serial i/o1 control registers 1, 2 ad/da control register serial i/o1 control registers 1, 2 (19) (18) (20) (21) (6) serial i/o1 function i/o d-a conversion output port pb input/output, individual bits input/output, individual bits serial i/o1 function i/o
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 17 fig. 11 port block diagram (1) ( 6 ) p o r t s p 7 0 t o p 7 2 , p 8 2 , p 9 0 , p b 6 i n t 0 , i n t 1 , i n t 2 i n t e r r u p t i n p u t c n t r 1 i n p u t s e r i a l i / o i n p u t p 9 0 ( 3 ) p o r t p 6 4 r x d i n p u t ( 4 ) p o r t s p 6 5 , p 6 6 t x d o r s c l k 2 1 o u t p u t p 6 6 ( 5 ) p o r t p 6 7 ( 2 ) p o r t s p 1 , p 3 , p 4 , p 5 , p 6 0 t o p 6 3 r e a d v e e p 4 , p 5 , p 6 0 t o p 6 3 ( 1 ) p o r t s p 0 , p 2 v e e d a t a b u s l o c a l d a t a b u s p o r t l a t c h d i m m e r s i g n a l ( n o t e 1 ) ? d a t a b u s l o c a l d a t a b u s d i m m e r s i g n a l ( n o t e 1 ) ? p o r t l a t c h f l d / p o r t s w i t c h r e g i s t e r d i r e c t i o n r e g i s t e r ( n o t e 2 ) p u l l - u p c o n t r o l d a t a b u s l o c a l d a t a b u s p o r t l a t c h f l d / p o r t s w i t c h r e g i s t e r d i r e c t i o n r e g i s t e r f l d / p o r t s w i t c h r e g i s t e r p o r t l a t c h d i r e c t i o n r e g i s t e r s e r i a l c l o c k i n p u t d a t a b u s l o c a l d a t a b u s d i m m e r s i g n a l ( n o t e 1 ) p u l l - u p c o n t r o l d i m m e r s i g n a l ( n o t e 1 ) p - c h a n n e l o u t p u t d i s a b l e s i g n a l ( p 6 5 ) o u t p u t o f f c o n t r o l s i g n a l p o r t l a t c h f l d / p o r t s w i t c h r e g i s t e r d i r e c t i o n r e g i s t e r d a t a b u s l o c a l d a t a b u s p u l l - u p c o n t r o l d i m m e r s i g n a l ( n o t e 1 ) s e r i a l r e a d y o u t p u t s r d y 2 o u t p u t e n a b l e b i t s e r i a l i / o 2 e n a b l e b i t s e r i a l c l o c k o u t p u t cl o c k i / o p i n s e l e c t i o n b i t s y n c h r o n o u s c l o c k s e l e c t i o n b i t s e r i a l c l o c k i n p u t d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r p u l l - u p c o n t r o l a - d c o n v e r s i o n i n p u t a n a l o g i n p u t p i n s e l e c t i o n b i t ? h i g h - b r e a k d o w n - v o l t a g e p - c h a n n e l t r a n s i s t o r n o t e s 1 : t h e d i m m e r s i g n a l s e t s t h e t o f f t i m i n g . 2 : a p u l l - d o w n r e s i s t o r i s n o t b u i l t i n t o p o r t s p 4 , p 5 a n d p 6 0 t o p 6 3 . s e r i a l i / o 2 s e l e c t i o n s i g n a l o u t p u t
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 18 fig. 12 port block diagram (2) ( 8 ) p o r t s p 7 4 t o p 7 6 t i m e r 1 o u t p u t s e l e c t i o n b i t t i m e r 3 o u t p u t s e l e c t i o n b i t t i m e r 6 o u t p u t s e l e c t i o n b i t ( 1 1 ) p o r t p 8 1 p o r t p 8 0 ( 1 0 ) p o r t p 8 0 ( 9 ) p o r t p 7 7 ( 1 3 ) p o r t s p 9 1 , p 9 2 s o u t o r s c l k p 9 2 ( 1 4 ) p o r t p 9 3 ( 7 ) p o r t p 7 3 i n t 3 i n t e r r u p t i n p u t ( 1 2 ) p o r t p 8 3 c n t r 0 , c n t r 2 i n p u t d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r d i m m e r o u t p u t c o n t r o l b i t d i m m e r s i g n a l o u t p u t p u l l - u p c o n t r o l p u l l - u p c o n t r o l d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r t i m e r 1 o u t p u t t i m e r 3 o u t p u t t i m e r 6 o u t p u t d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r b u z z e r c o n t r o l s i g n a l p u l l - u p c o n t r o l b u z z e r s i g n a l o u t p u t i n t 4 i n t e r r u p t i n p u t d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r p u l l - u p c o n t r o l p o r t x c s w i t c h b i t s u b - c l o c k g e n e r a t i n g c i r c u i t i n p u t p o r t x c s w i t c h b i t d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r p u l l - u p c o n t r o l p o r t x c s w i t c h b i t o s c i l l a t o r d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r t i m e r x o p e r a t i n g m o d e b i t s t i m e r x o u t p u t p u l l - u p c o n t r o l s r d y 3 o u t p u t e n a b l e b i t p u l l - u p c o n t r o l d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r s e r i a l r e a d y o u t p u t a - d c o n v e r s i o n i n p u t a n a l o g i n p u t p i n s e l e c t i o n b i t s d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r p - c h a n n e l o u t p u t d i s a b l e s i g n a l ( p 9 1 ) o u t p u t o f f c o n t r o l s i g n a l s e r i a l i / o 3 s e l e c t i o n s i g n a l p u l l - u p c o n t r o l s e r i a l c l o c k i n p u t a - d c o n v e r s i o n i n p u t a n a l o g i n p u t p i n s e l e c t i o n b i t s
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 19 fig. 13 port block diagram (3) ( 1 5 ) p o r t s p 9 4 , p 9 5 r t p o u t p u t ( 1 6 ) p o r t s p 9 6 , p 9 7 (20) port pb 3 s stb1 output ( 1 8 ) p o r t s p b 0 , p b 2 serial clock input s busy1 input s clk12 output s busy1 out p ut p b 0 ( 1 7 ) p o r t p a (19) port pb 1 ( 2 1 ) p o r t s p b 4 , p b 5 s o u t o r s c l k p b 4 d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r p u l l - u p c o n t r o l r e a l t i m e p o r t c o n t r o l b i t a - d c o n v e r s i o n i n p u t a n a l o g i n p u t p i n s e l e c t i o n b i t s d a t a b u s port latch d i r e c t i o n r e g i s t e r pwm output selection bit buzzer control signal p u l l - u p c o n t r o l a-d conversion input analog input pin selection bits pwm output buzzer signal output d a t a b u s port latch direction register p u l l - u p c o n t r o l a - d c o n v e r s i o n i n p u t a n a l o g i n p u t p i n s e l e c t i o n b i t s s e r i a l i / o 1 s e l e c t i o n s i g n a l p b 1 / s r d y 1 p b 2 / s b u s y 1 p i n c o n t r o l b i t d - a c o n v e r t e r o u t p u t d - a o u t p u t e n a b l e b i t data bus port latch d i r e c t i o n r e g i s t e r p u l l - u p c o n t r o l p u l l - u p c o n t r o l pb 1 /s rdy1 ?b 2 /s busy1 pin control bit d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r serial ready output serial ready input pb 3 /s stb1 pin control bit d a t a b u s p o r t l a t c h direction register pull-up control d a t a b u s port latch d i r e c t i o n r e g i s t e r p u l l - u p c o n t r o l p-channel output disable signal (pb 5 ) output off control signal serial i/o1 selection signal s e r i a l c l o c k i n p u t
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 20 interrupts interrupts occur by twenty two sources: five external, sixteen inter- nal, and one software. interrupt control each interrupt except the brk instruction interrupt has both an inter- rupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. an interrupt occurs if the corresponding inter- rupt request and enable bits are 1 and the interrupt disable flag is 0. interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by soft- ware. the brk instruction interrupt and reset cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruction interrupt and reset. if several interrupts requests occur at the same time, the interrupt with highest priority is accepted first. interrupt operation upon acceptance of an interrupt the following operations are auto- matically performed: 1. the contents of the program counter and processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. interrupt source selection any of the following interrupt sources can be selected by the inter- rupt source switch register (address 0039 16 ). 1. int 1 or serial i/o3 2. int 3 or serial i/o2 transmit 3. int 4 or a-d conversion note when the active edge of an external interrupt (int 0 int 4 ) is set or when switching interrupt sources in the same vector address, the corresponding interrupt request bit may also be set. therefore, please take following sequence: (1) disable the external interrupt which is selected. (2) change the active edge in interrupt edge selection register (3) clear the set interrupt request bit to 0. (4) enable the external interrupt which is selected.
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 21 vector addresses (note 1) interrupt request interrupt source priority remarks high low generating conditions reset (note 2) 1 fffd 16 fffc 16 at reset non-maskable int 0 2 fffb 16 fffa 16 at detection of either rising or falling edge of external interrupt int 0 input (active edge selectable) int 1 3 fff9 16 fff8 16 at detection of either rising or falling edge of external interrupt int 1 input (active edge selectable) valid when int 1 interrupt is selected serial i/o3 at completion of data transfer valid when serial i/o3 is selected int 2 4 fff7 16 fff6 16 at detection of either rising or falling edge of external interrupt int 2 input (active edge selectable) remote control/ at 8-bit counter overflow valid when interrupt interval counter overflow determination is operating serial i/o1 5 fff5 16 fff4 16 at completion of data transfer valid when serial i/o ordinary mode is selected serial i/o auto- at completion of the last data transfer valid when serial i/o automatic matic transfer transfer mode is selected timer x 6 fff3 16 fff2 16 at timer x underflow timer 1 7 fff1 16 fff0 16 at timer 1 underflow timer 2 8 ffef 16 ffee 16 at timer 2 underflow stp release timer underflow timer 3 9 ffed 16 ffec 16 at timer 3 underflow timer 4 10 ffeb 16 ffea 16 at timer 4 underflow timer 5 11 ffe9 16 ffe8 16 at timer 5 underflow timer 6 12 ffe7 16 ffe6 16 at timer 6 underflow serial i/o2 receive 13 ffe5 16 ffe4 16 at completion of serial i/o2 data receive int 3 14 ffe3 16 ffe2 16 at detection of either rising or falling edge of external interrupt int 3 input (active edge selectable) valid when int 3 interrupt is selected serial i/o2 transmit at completion of serial i/o2 data transmit int 4 15 ffe1 16 ffe0 16 at detection of either rising or falling edge of external interrupt int 4 input (active edge selectable) valid when int 4 interrupt is selected a-d conversion at completion of a-d conversion valid when a-d conversion is selected fld blanking 16 ffdf 16 ffde 16 at falling edge of the last timing immediately valid when fld blanking before blanking period starts interrupt is selected fld digit at rising edge of digit (each timing) valid when fld digit interrupt is selected brk instruction 17 ffdd 16 ffdc 16 at brk instruction execution non-maskable software interrupt table 8 interrupt vector addresses and priority notes 1 : vector addresses contain interrupt jump destination addresses. 2 : reset function in the same way as an interrupt with the highest priority.
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 22 fig. 15 structure of interrupt related registers fig. 14 interrupt control b 7 b 7 b 7 b 7 b 7 b 7 b 0 b 0 b 0 b 0 b 0 b 0 i n t 0 i n t e r r u p t e n a b l e b i t i n t 1 i n t e r r u p t e n a b l e b i t s e r i a l i / o 3 i n t e r r u p t e n a b l e b i t i n t 2 i n t e r r u p t e n a b l e b i t r e m o t e c o n t r o l l e r / c o u n t e r o v e r f l o w i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 i n t e r r u p t e n a b l e b i t s e r i a l i / o a u t o m a t i c t r a n s f e r i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t t i m e r 1 i n t e r r u p t e n a b l e b i t t i m e r 2 i n t e r r u p t e n a b l e b i t t i m e r 3 i n t e r r u p t e n a b l e b i t i n t 0 i n t e r r u p t r e q u e s t b i t i n t 1 i n t e r r u p t r e q u e s t b i t s e r i a l i / o 3 i n t e r r u p t r e q u e s t b i t i n t 2 i n t e r r u p t r e q u e s t b i t r e m o t e c o n t r o l l e r / c o u n t e r o v e r f l o w i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 i n t e r r u p t r e q u e s t b i t s e r i a l i / o a u t o m a t i c t r a n s f e r i n t e r r u p t r e q u e s t b i t t i m e r x i n t e r r u p t r e q u e s t b i t t i m e r 1 i n t e r r u p t r e q u e s t b i t t i m e r 2 i n t e r r u p t r e q u e s t b i t t i m e r 3 i n t e r r u p t r e q u e s t b i t i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r i n t 0 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 1 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 2 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 3 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 4 i n t e r r u p t e d g e s e l e c t i o n b i t n o t u s e d ( r e t u r n 0 w h e n r e a d ) c n t r 0 p i n e d g e s w i t c h b i t c n t r 1 p i n e d g e s w i t c h b i t ( i n t e d g e : a d d r e s s 0 0 3 a 1 6 ) 0 : f a l l i n g e d g e a c t i v e 1 : r i s i n g e d g e a c t i v e i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t e r r u p t c o n t r o l r e g i s t e r 1 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d ( i r e q 1 : a d d r e s s 0 0 3 c 1 6 ) ( i c o n 1 : a d d r e s s 0 0 3 e 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 : a d d r e s s 0 0 3 d 1 6 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d ( i c o n 2 : a d d r e s s 0 0 3 f 1 6 ) i n t e r r u p t s o u r c e s w i t c h r e g i s t e r i n t 3 / s e r i a l i / o 2 t r a n s m i t i n t e r r u p t s w i t c h b i t 0 : i n t 3 i n t e r r u p t 1 : s e r i a l i / o 2 t r a n s m i t i n t e r r u p t i n t 4 / a d c o n v e r s i o n i n t e r r u p t s w i t c h b i t 0 : i n t 4 i n t e r r u p t 1 : a - d c o n v e r s i o n i n t e r r u p t i n t 1 / s e r i a l i / o 3 i n t e r r u p t s w i t c h b i t 0 : i n t 1 i n t e r r u p t 1 : se r i a l i / o 3 i n t e r r u p t n o t u s e d ( r e t u r n 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h e s e b i t s . ) ( i f r : a d d r e s s 0 0 3 9 1 6 ) 0 : r i s i n g e d g e c o u n t 1 : f a l l i n g e d g e c o u n t i n t 3 / s e r i a l i / o 2 t r a n s m i t i n t e r r u p t e n a b l e b i t i n t 4 i n t e r r u p t e n a b l e b i t a d c o n v e r s i o n i n t e r r u p t e n a b l e b i t f l d b l a n k i n g i n t e r r u p t e n a b l e b i t f l d d i g i t i n t e r r u p t e n a b l e b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t . ) i n t 3 / s e r i a l i / o 2 t r a n s m i t i n t e r r u p t r e q u e s t b i t i n t 4 i n t e r r u p t r e q u e s t b i t a d c o n v e r s i o n i n t e r r u p t r e q u e s t b i t f l d b l a n k i n g i n t e r r u p t r e q u e s t b i t f l d d i g i t i n t e r r u p t r e q u e s t b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) t i m e r 4 i n t e r r u p t r e q u e s t b i t t i m e r 5 i n t e r r u p t r e q u e s t b i t t i m e r 6 i n t e r r u p t r e q u e s t b i t s e r i a l i / o 2 r e c e i v e i n t e r r u p t r e q u e s t b i t t i m e r 4 i n t e r r u p t e n a b l e b i t t i m e r 5 i n t e r r u p t e n a b l e b i t t i m e r 6 i n t e r r u p t e n a b l e b i t s e r i a l i / o 2 r e c e i v e i n t e r r u p t e n a b l e b i t interrupt disable flag i interrupt request interrupt request bit interrupt enable bit brk instruction reset
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 23 timers 8-bit timer the 38b7 group has six built-in 8-bit timers : timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. each timer has the 8-bit timer latch. all timers are down-counters. when the timer reaches 00 16 , an underflow occurs with the next count pulse. then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. when a timer underflows, the interrupt request bit corresponding to that timer is set to 1 . the count can be stopped by setting the stop bit of each timer to 1 . the internal system clock can be set to either the high-speed mode or low-speed mode with the cpu mode register. at the same time, the timer internal count source is switched to either f(x in ) or f(x cin ). timer 1, timer 2 the count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. a rectangular waveform of timer 1 under- flow signal divided by 2 can be output from the p7 5 /t1 out pin. the active edge of the external clock cntr 0 can be switched with the bit 6 of the interrupt edge selection register. at reset or when executing the stp instruction, all bits of the timer 12 mode register are cleared to 0 , timer 1 is set to ff 16 , and timer 2 is set to 01 16 . timer 3, timer 4 the count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. a rectangular waveform of timer 3 under- flow signal divided by 2 can be output from the p7 6 /t3 out pin. the active edge of the external clock cntr 1 can be switched with the bit 7 of the interrupt edge selection register. timer 5, timer 6 the count sources of timer 5 and timer 6 can be selected by setting the timer 56 mode register. a rectangular waveform of timer 6 under- flow signal divided by 2 can be output from the p7 4 /pwm 1 pin. timer 6 pwm 1 mode timer 6 can output a pwm rectangular waveform with h duty cycle n/(n+m) from the p7 4 /pwm 1 pin by setting the timer 56 mode regis- ter (refer to figure 18). the n is the value set in timer 6 latch (address 0025 16 ) and m is the value in the timer 6 pwm register (address 0027 16 ). if n is 0, the pwm output is l , if m is 0 , the pwm output is h (n = 0 is prior than m = 0). in the pwm mode, interrupts occur at the rising edge of the pwm output. fig. 16 structure of timer related registers t i m e r 1 2 m o d e r e g i s t e r ( t 1 2 m : a d d r e s s 0 0 2 8 1 6 ) t i m e r 1 c o u n t s t o p b i t 0 : c o u n t o p e r a t i o n 1 : c o u n t s t o p t i m e r 2 c o u n t s t o p b i t 0 : c o u n t o p e r a t i o n 1 : c o u n t s t o p t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 0 1 : f ( x c i n ) 1 0 : f ( x i n ) / 1 6 o r f ( x c i n ) / 3 2 1 1 : f ( x i n ) / 6 4 o r f ( x c i n ) / 1 2 8 t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : u n d e r f l o w o f t i m e r 1 0 1 : f ( x c i n ) 1 0 : e x t e r n a l c o u n t i n p u t c n t r 0 1 1 : n o t a v a i l a b l e t i m e r 1 o u t p u t s e l e c t i o n b i t ( p 7 5 ) 0 : i / o p o r t 1 : t i m e r 1 o u t p u t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t . ) t i m e r 3 4 m o d e r e g i s t e r ( t 3 4 m : a d d r e s s 0 0 2 9 1 6 ) t i m e r 3 c o u n t s t o p b i t 0 : c o u n t o p e r a t i o n 1 : c o u n t s t o p t i m e r 4 c o u n t s t o p b i t 0 : c o u n t o p e r a t i o n 1 : c o u n t s t o p t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 0 1 : u n d e r f l o w o f t i m e r 2 1 0 : f ( x i n ) / 1 6 o r f ( x c i n ) / 3 2 1 1 : f ( x i n ) / 6 4 o r f ( x c i n ) / 1 2 8 t i m e r 4 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 0 1 : u n d e r f l o w o f t i m e r 3 1 0 : e x t e r n a l c o u n t i n p u t c n t r 1 1 1 : n o t a v a i l a b l e t i m e r 3 o u t p u t s e l e c t i o n b i t ( p 7 6 ) 0 : i / o p o r t 1 : t i m e r 3 o u t p u t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t . ) t i m e r 5 6 m o d e r e g i s t e r ( t 5 6 m : a d d r e s s 0 0 2 a 1 6 ) t i m e r 5 c o u n t s t o p b i t 0 : c o u n t o p e r a t i o n 1 : c o u n t s t o p t i m e r 6 c o u n t s t o p b i t 0 : c o u n t o p e r a t i o n 1 : c o u n t s t o p t i m e r 5 c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 1 : u n d e r f l o w o f t i m e r 4 t i m e r 6 o p e r a t i o n m o d e s e l e c t i o n b i t 0 : t i m e r m o d e 1 : p w m m o d e t i m e r 6 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 0 1 : u n d e r f l o w o f t i m e r 5 1 0 : u n d e r f l o w o f t i m e r 4 1 1 : n o t a v a i l a b l e t i m e r 6 ( p w m ) o u t p u t s e l e c t i o n b i t ( p 7 4 ) 0 : i / o p o r t 1 : t i m e r 6 o u t p u t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t . ) b 7 b 0 b 7 b 0 b 7 b 0
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 24 fig. 17 block diagram of timer x i n 1 / 8 p 7 6 / t 3 o u t 1 / 2 x c i n 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 p 7 5 / t 1 o u t 1 / 2 p 8 3 / c n t r 0 / c n t r 2 1 0 1 / 2 p w m p 7 4 / p w m 1 1 0 p 8 2 / c n t r 1 1 / 6 4 1 / 2 1 1 1 1 1 / 1 6 1 0 1 0 i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t s t i m e r 1 i n t e r r u p t r e q u e s t d a t a b u s t i m e r 1 l a t c h ( 8 ) t i m e r 1 ( 8 ) f f 1 6 t i m e r 1 c o u n t s t o p b i t r e s e t s t p i n s t r u c t i o n p 7 5 l a t c h t i m e r 1 o u t p u t s e l e c t i o n b i t p 7 5 d i r e c t i o n r e g i s t e r t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t s t i m e r 2 l a t c h ( 8 ) t i m e r 2 ( 8 ) t i m e r 2 c o u n t s t o p b i t 0 1 1 6 t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t s t i m e r 3 l a t c h ( 8 ) t i m e r 3 ( 8 ) t i m e r 3 c o u n t s t o p b i t t i m e r 2 i n t e r r u p t r e q u e s t t i m e r 3 i n t e r r u p t r e q u e s t p 7 6 l a t c h r i s i n g / f a l l i n g a c t i v e e d g e s w i t c h t i m e r 3 o u t p u t s e l e c t i o n b i t p 7 6 d i r e c t i o n r e g i s t e r t i m e r 4 c o u n t s o u r c e s e l e c t i o n b i t s t i m e r 4 l a t c h ( 8 ) t i m e r 4 ( 8 ) t i m e r 4 c o u n t s t o p b i t r i s i n g / f a l l i n g a c t i v e e d g e s w i t c h t i m e r 4 i n t e r r u p t r e q u e s t t i m e r 5 c o u n t s o u r c e s e l e c t i o n b i t t i m e r 5 l a t c h ( 8 ) t i m e r 5 ( 8 ) t i m e r 5 c o u n t s t o p b i t t i m e r 5 i n t e r r u p t r e q u e s t p 7 4 l a t c h t i m e r 6 o u t p u t s e l e c t i o n b i t p 7 4 d i r e c t i o n r e g i s t e r t i m e r 6 c o u n t s o u r c e s e l e c t i o n b i t s t i m e r 6 l a t c h ( 8 ) t i m e r 6 ( 8 ) t i m e r 6 c o u n t s t o p b i t t i m e r 6 p w m r e g i s t e r ( 8 ) t i m e r 6 o p e r a t i o n m o d e s e l e c t i o n b i t t i m e r 6 i n t e r r u p t r e q u e s t c n t r 0 c n t r 2
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 25 fig. 18 timing chart of timer 6 pwm 1 mode t s t i m e r 6 c o u n t s o u r c e t i m e r 6 p w m m o d e n ? t s ( n + m ) ? t s t i m e r 6 i n t e r r u p t r e q u e s t n o t e : p w m w a v e f o r m ( d u t y : n / ( n + m ) a n d p e r i o d : ( n + m ) ? t s ) i s o u t p u t . n : s e t t i n g v a l u e o f t i m e r 6 m : s e t t i n g v a l u e o f t i m e r 6 p w m r e g i s t e r t s : p e r i o d o f t i m e r 6 c o u n t s o u r c e m ? t s t i m e r 6 i n t e r r u p t r e q u e s t
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 26 16-bit timer timer x is a 16-bit timer that can be selected in one of four modes by the timer x mode registers 1, 2 and can be controlled for the timer x write and the real time port by setting the timer x mode registers. read and write operation on 16-bit timer must be performed for both high- and low-order bytes. when reading a 16-bit timer, read from the high-order byte first. when writing to 16-bit timer, write to the low- order byte first. the 16-bit timer cannot perform the correct operation when reading during write operation, or when writing during read operation. timer x timer x is a down-counter. when the timer reaches 0000 16 , an underflow occurs with the next count pulse. then the contents of the timer latch is reloaded into the timer and the timer continues down- counting. when a timer underflows, the interrupt request bit corre- sponding to that timer is set to 1 . (1) timer mode a count source can be selected by setting the timer x count source selection bits (bits 1 and 2) of the timer x mode register 1. (2) pulse output mode each time the timer underflows, a signal output from the cntr 2 pin is inverted. except for this, the operation in pulse output mode is the same as in timer mode. when using a timer in this mode, set the port shared with the cntr 2 pin to output. (3) event counter mode the timer counts signals input through the cntr 2 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the port shared with the cntr 2 pin to input. (4) pulse width measurement mode a count source can be selected by setting the timer x count source selection bits (bits 1 and 2) of the timer x mode register 1. when cntr 2 active edge switch bit is 0 , the timer counts while the input signal of the cntr 2 pin is at h . when it is 1 , the timer counts while the input signal of the cntr 2 pin is at l . when using a timer in this mode, set the port shared with the cntr 2 pin to input. note ?imer x write control if the timer x write control bit is 0 , when the value is written in the address of timer x, the value is loaded in the timer x and the latch at the same time. if the timer x write control bit is 1 , when the value is written in the address of timer x, the value is loaded only in the latch. the value in the latch is loaded in timer x after timer x underflows. when the value is written in latch only, unexpected value may be set in the high-order counter if the writing in high-order latch and the underflow of timer x are performed at the same timing. ?eal time port control while the real time port function is valid, data for the real time port are output from ports p9 4 and p9 5 each time the timer x underflows. (however, if the real time port control bit is changed from 0 to 1 , data are output independent of the timer x.) when the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer x. before using this function, set the corresponding port direction regis- ters to output mode.
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 27 fig. 20 structure of timer x related registers fig. 19 block diagram of timer x b 7b 6b 5b 4b 3 b 2b 1b 0 r e a l t i m e p o r t c o n t r o l b i t ( p 9 4 ) 0 : r e a l t i m e p o r t f u n c t i o n i s i n v a l i d 1 : r e a l t i m e p o r t f u n c t i o n i s v a l i d r e a l t i m e p o r t c o n t r o l b i t ( p 9 5 ) 0 : r e a l t i m e p o r t f u n c t i o n i s i n v a l i d 1 : r e a l t i m e p o r t f u n c t i o n i s v a l i d p 9 4 d a t a f o r r e a l t i m e p o r t p 9 5 d a t a f o r r e a l t i m e p o r t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) t i m e r x m o d e r e g i s t e r 1 ( t x m 1 : a d d r e s s 0 0 2 e 1 6 ) t i m e r x w r i t e c o n t r o l b i t 0 : w r i t e d a t a t o b o t h t i m e r l a t c h a n d t i m e r 1 : w r i t e d a t a t o t i m e r l a t c h o n l y t i m e r x c o u n t s o u r c e s e l e c t i o n b i t s b 2 b 1 00 : f ( x i n ) / 2 o r f ( x c i n ) / 4 01 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 10 : f ( x i n ) / 6 4 o r f ( x c i n ) / 1 2 8 11 : n o t a v a i l a b l e n o t u s e d ( r e t u r n s 0 w h e n r e a d ) t i m e r x o p e r a t i n g m o d e b i t s b 5 b 4 00 : t i m e r m o d e 01 : p u l s e o u t p u t m o d e 10 : e v e n t c o u n t e r m o d e 11 : p u l s e w i d t h m e a s u r e m e n t m o d e c n t r 2 a c t i v e e d g e s w i t c h b i t 0 : e v e n t c o u n t e r m o d e ; c o u n t s r i s i n g e d g e s p u l s e o u t p u t m o d e ; o u t p u t s t a r t s w i t h h l e v e l p u l s e w i d t h m e a s u r e m e n t m o d e ; m e a s u r e s h p e r i o d s 1 : e v e n t c o u n t e r m o d e ; c o u n t s f a l l i n g e d g e s p u l s e o u t p u t m o d e ; o u t p u t s t a r t s w i t h l l e v e l p u l s e w i d t h m e a s u r e m e n t m o d e ; m e a s u r e s l p e r i o d s t i m e r x s t o p c o n t r o l b i t 0 : c o u n t o p e r a t i n g 1 : c o u n t s t o p t i m e r x m o d e r e g i s t e r 2 ( t x m 2 : a d d r e s s 0 0 2 f 1 6 ) b 7b 6b 5b 4b 3 b 2b 1 b 0 c n t r 2 a c t i v e e d g e s w i t c h b i t c n t r 2 a c t i v e e d g e s w i t c h b i t r e a l t i m e p o r t c o n t r o l b i t r e a l t i m e p o r t c o n t r o l b i t s 0 ? 0 1 1 0 0 0 , 0 1 , 1 1 q q t p8 3 /cntr 0 /cntr 2 cntr 0 1 0 1 0 ? 0 q d q d p9 4 p9 5 ? 0 x i n x c i n 1 0 1 / 2 1 / 2 1 / 8 1 / 6 4 p 8 3 l a t c h timer x ( low-order ) ( 8 ) timer x ( hi g h-order ) ( 8 ) t i m e r x l a t c h ( h i g h - o r d e r ) ( 8 ) t i m e r x l a t c h ( l o w - o r d e r ) ( 8 ) data bus p u l s e o u t p u t m o d e p 8 3 d i r e c t i o n r e g i s t e r pulse width measurement mode t i m e r x o p e r a t i n g m o d e b i t s timer x stop control bit pulse output mode c o u n t s o u r c e s e l e c t i o n b i t i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t d i v i d e r t i m e r x w r i t e c o n t r o l b i t t i m e r x i n t e r r u p t r e q u e s t timer x mode register write signal p 9 5 l a t c h p 9 5 d i r e c t i o n r e g i s t e r p 9 4 l a t c h p 9 4 d i r e c t i o n r e g i s t e r latch l a t c h p 9 4 d a t a f o r r e a l t i m e p o r t r e a l t i m e p o r t c o n t r o l b i t ( p 9 4 ) p9 5 data for real time port r e a l t i m e p o r t c o n t r o l b i t ( p 9 5 ) t i m e r x m o d e r e g i s t e r w r i t e s i g n a l
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 28 serial i/o serial i/o1 serial i/o1 is used as the clock synchronous serial i/o and has an ordinary mode and an automatic transfer mode. in the automatic transfer mode, serial transfer is performed through the serial i/o automatic transfer ram which has up to 256 bytes (addresses fig. 21 block diagram of serial i/o1 0f00 16 to 0fff 16 ). the pb 1 /s rdy1 , pb 2 /s busy1 , and pb3/s stb1 pins each have a handshake i/o signal function and can select either h active or l active for active logic. main data bus s er i a l i / o 1 automatic transfer controller l o c a l d a t a b u s serial i/o automatic transfer ram (0f00 16 to 0fff 16 ) s e r i a l i / o 1 c o n t r o l r e g i s t e r 3 x c i n x i n internal system clock selection bit s er i a l i / o 1 automatic transfer data p ointer address decoder m a i n a d d r e s s b u s local address bus 1 0 1/8 1/16 1/32 1 / 6 4 1 / 1 2 8 s e r i a l i / o 1 i n t e r r u p t r e q u e s t pb 2 latch serial i/o1 counter s y n c h r o n o u s c i r c u i t s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t 1 p b 1 l a t c h p b 4 / s c l k 1 1 0 1 s c l k 1 0 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s 1/256 pb 3 latch p b 2 / s b u s y 1 p b 3 / s s t b 1 ( p b 3 / s s t b 1 p i n c o n t r o l b i t ) s e r i a l t r a n s f e r s t a t u s f l a g 0 1 0 1 p b 1 / s r d y 1 0 1 p b 4 l a t c h pb 5 /s out1 p b 6 / s i n 1 pb 5 latch serial i/o1 re g ister (8) 0 1 s e r i a l t r a n s f e r s e l e c t i o n b i t s 1 / 2 d i v i d e r 1 / 4 serial i/o1 clock p in selection bit p b 0 / s c l k 1 2 1 0 pb 0 latch 0 1 0 1 s e r i a l i / o 1 c l o c k p i n s e l e c t i o n b i t s p b 1 / s r d y 1 p b 2 / s b u s y 1 p i n c o n t r o l b i t pb 1 /s rdy1 pb 2 /s busy1 pin control bit
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 29 fig. 22 structure of serial i/o1 control registers 1, 2 b 7b 6b 5b 4b 3b 2b 1b 0 b 7b 6b 5b 4b 3b 2b 1b 0 p b 1 / s r d y 1 p b 2 / s b u s y 1 p i n c o n t r o l b i t s b 3 b 2 b 1 b 0 0 0 0 0 : p i n s p b 1 a n d p b 2 a r e i / o p o r t s 0 0 0 1 : n o t u s e d 0 0 1 0 : p b 1 p i n i s a n s r d y 1 o u t p u t , p b 2 p i n i s a n i / o p o r t . 0 0 1 1 : p b 1 p i n i s a n s r d y 1 o u t p u t , p b 2 p i n i s a n i / o p o r t . 0 1 0 0 : p b 1 p i n i s a n i / o p o r t , p b 2 p i n i s a n s b u s y 1 i n p u t . 0 1 0 1 : p b 1 p i n i s a n i / o p o r t , p b 2 p i n i s a n s b u s y 1 i n p u t . 0 1 1 0 : p b 1 p i n i s a n i / o p o r t , p b 2 p i n i s a n s b u s y 1 o u t p u t . 0 1 1 1 : p b 1 p i n i s a n i / o p o r t , p b 2 p i n i s a n s b u s y 1 o u t p u t . 1 0 0 0 : p b 1 p i n i s a n s r d y 1 i n p u t , p b 2 p i n i s a n s b u s y 1 o u t p u t . 1 0 0 1 : p b 1 p i n i s a n s r d y 1 i n p u t , p b 2 p i n i s a n s b u s y 1 o u t p u t . 1 0 1 0 : p b 1 p i n i s a n s r d y 1 i n p u t , p b 2 p i n i s a n s b u s y 1 o u t p u t . 1 0 1 1 : p b 1 p i n i s a n s r d y 1 i n p u t , p b 2 p i n i s a n s b u s y 1 o u t p u t . 1 1 0 0 : p b 1 p i n i s a n s r d y 1 o u t p u t , p b 2 p i n i s a n s b u s y 1 i n p u t . 1 1 0 1 : p b 1 p i n i s a n s r d y 1 o u t p u t , p b 2 p i n i s a n s b u s y 1 i n p u t . 1 1 1 0 : p b 1 p i n i s a n s r d y 1 o u t p u t , p b 2 p i n i s a n s b u s y 1 i n p u t . 1 1 1 1 : p b 1 p i n i s a n s r d y 1 o u t p u t , p b 2 p i n i s a n s b u s y 1 i n p u t . s b u s y 1 o u t p u t s s t b 1 o u t p u t f u n c t i o n s e l e c t i o n b i t ( v a l i d i n a u t o m a t i c t r a n s f e r m o d e ) 0 : f u n c t i o n s a s e a c h 1 - b y t e s i g n a l 1 : f u n c t i o n s a s s i g n a l f o r a l l t r a n s f e r d a t a s e r i a l t r a n s f e r s t a t u s f l a g 0 : s e r i a l t r a n s f e r c o m p l e t i o n 1 : s e r i a l t r a n s f e r r i n g s o u t 1 p i n c o n t r o l b i t ( a t n o - t r a n s f e r s e r i a l d a t a ) 0 : o u t p u t a c t i v e 1 : o u t p u t h i g h - i m p e d a n c e p b 5 / s o u t 1 p - c h a n n e l o u t p u t d i s a b l e b i t 0 : c m o s 3 - s t a t e ( p - c h a n n e l o u t p u t i s v a l i d . ) 1 : n - c h a n n e l o p e n - d r a i n ( p - c h a n n e l o u t p u t i s i n v a l i d . ) s e r i a l i / o 1 c o n t r o l r e g i s t e r 2 ( s i o 1 c o n 2 ( s c 1 2 ) : a d d r e s s 0 0 1 a 1 6 ) s e r i a l i / o 1 c o n t r o l r e g i s t e r 1 ( s i o 1 c o n 1 ( s c 1 1 ) : a d d r e s s 0 0 1 9 1 6 ) s e r i a l t r a n s f e r s e l e c t i o n b i t s b 1 b 0 0 0 : s e r i a l i / o d i s a b l e d ( p i n s p b 0 t o p b 6 a r e i / o p o r t s ) 0 1 : 8 - b i t s e r i a l i / o 1 0 : n o t a v a i l a b l e 1 1 : a u t o m a t i c t r a n s f e r s e r i a l i / o ( 8 - b i t s ) s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t s ( p b 3 / s s t b 1 p i n c o n t r o l b i t ) b 3 b 2 0 0 : i n t e r n a l s y n c h r o n o u s c l o c k ( p b 3 p i n i s a n i / o p o r t . ) 0 1 : e x t e r n a l s y n c h r o n o u s c l o c k ( p b 3 p i n i s a n i / o p o r t . ) 1 0 : i n t e r n a l s y n c h r o n o u s c l o c k ( p b 3 p i n i s a n s s t b 1 o u t p u t . ) 1 1 : i n t e r n a l s y n c h r o n o u s c l o c k ( p b 3 p i n i s a n s s t b 1 o u t p u t . ) s e r i a l i / o i n i t i a l i z a t i o n b i t 0 : s e r i a l i / o i n i t i a l i z a t i o n 1 : s e r i a l i / o e n a b l e d t r a n s f e r m o d e s e l e c t i o n b i t 0 : f u l l d u p l e x ( t r a n s m i t a n d r e c e i v e ) m o d e ( p b 6 p i n i s a n s i n 1 i n p u t . ) 1 : t r a n s m i t - o n l y m o d e ( p b 6 p i n i s a n i / o p o r t . ) t r a n s f e r d i r e c t i o n s e l e c t i o n b i t 0 : l s b f i r s t 1 : m s b f i r s t s e r i a l i / o 1 c l o c k p i n s e l e c t i o n b i t 0 : s c l k 1 1 ( p b 0 / s c l k 1 2 p i n i s a n i / o p o r t . ) 1 : s c l k 1 2 ( p b 4 / s c l k 1 1 p i n i s a n i / o p o r t . )
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 30 (1) serial i/o1 operation either the internal synchronous clock or external synchronous clock can be selected by the serial i/o1 synchronous clock selec- tion bits (b2 and b3 of address 0019 16 ) of serial i/o1 control register 1 as synchronous clock for serial transfer. the internal synchronous clock has a built-in dedicated divider where 7 different clocks are selected by the internal synchronous clock selection bits (b5, b6 and b7 of address 001c 16 ) of serial i/o1 control register 3. the pb 1 /s rdy1 , pb 2 /s busy1 , and pb 3 /s stb1 pins each select ei- ther i/o port or handshake i/o signal by the serial i/o1 synchronous clock selection bits (b2 and b3 of address 0019 16 ) of serial i/o1 control register 1 as well as the pb 1 /s rdy1 pb 2 / s busy1 pin control bits (b0 to b3 of address 001a 16 ) of serial i/o1 control register 2. for the sout 1 being used as an output pin, either cmos output or n-channel open-drain output is selected by the pb 5 /s out1 p- channel output disable bit (b7 of address 001a 16 ) of serial i/o1 control register 2. either output active or high-impedance can be selected as a s out1 pin state at serial non-transfer by the s out1 pin control bit (b6 of address 001a 16 ) of serial i/o1 control register 2. however, when the external synchronous clock is selected, perform the fol- lowing setup to put the s out1 pin into a high-impedance state: when the s clk1 input is h after completion of transfer, set the s out1 pin control bit to 1 . when the s clk1 input goes to l after the start of the next serial transfer, the s out1 pin control bit is automatically reset to 0 and put into an output active state. regardless of whether the internal synchronous clock or external synchronous clock is selected, the full duplex mode and the trans- mit-only mode are available for serial transfer, one of which is selected by the transfer mode selection bit (b5 of address 0019 16 ) of serial i/o1 control register 1. either lsb first or msb first is selected for the i/o sequence of the serial transfer bit strings by the transfer direction selection bit (b6 of address 0019 16 ) of serial i/o1 control register 1. when using serial i/o1, first select either 8-bit serial i/o or auto- matic transfer serial i/o by the serial transfer selection bits (b0 and b1 of address 0019 16 ) of serial i/o1 control register 1, after completion of the above bit setup. next, set the serial i/o initializa- tion bit (b4 of address 0019 16 ) of serial i/o1 control register 1 to 1 (serial i/o enable) . when stopping serial transfer while data is being transferred, re- gardless of whether the internal or external synchronous clock is selected, reset the serial i/o initialization bit (b4) to 0 . fig. 23 structure of serial i/o1 control register 3 b 7b 6 b 5 b 4b 3b 2b 1b 0 s e r i a l i / o 1 c o n t r o l r e g i s t e r 3 ( s i o 1 c o n 3 ( s c 1 3 ) : a d d r e s s 0 0 1 c 1 6 ) a u t o m a t i c t r a n s f e r i n t e r v a l s e t b i t s b 4 b 3 b 2 b 1 b 0 0 0 0 0 0 : 2 c y c l e s o f t r a n s f e r c l o c k s 0 0 0 0 1 : 3 c y c l e s o f t r a n s f e r c l o c k s : 1 1 1 1 0 : 3 2 c y c l e s o f t r a n s f e r c l o c k s 1 1 1 1 1 : 3 3 c y c l e s o f t r a n s f e r c l o c k s d a t a i s w r i t t e n t o a l a t c h a n d r e a d f r o m a d e c r e m e n t c o u n t e r . i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s b 7 b 6 b 5 0 0 0 : f ( x i n ) / 4 o r f ( x c i n ) / 8 0 0 1 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 0 1 0 : f ( x i n ) / 1 6 o r f ( x c i n ) / 3 2 0 1 1 : f ( x i n ) / 3 2 o r f ( x c i n ) / 6 4 1 0 0 : f ( x i n ) / 6 4 o r f ( x c i n ) / 1 2 8 1 0 1 : f ( x i n ) / 1 2 8 o r f ( x c i n ) / 2 5 6 1 1 0 : f ( x i n ) / 2 5 6 o r f ( x c i n ) / 5 1 2
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 31 (2) 8-bit serial i/o mode address 001b 16 is assigned to the serial i/o1 register. when the internal synchronous clock is selected, a serial transfer of the 8-bit serial i/o is started by a write signal to the serial i/o1 register (address 001b 16 ). the serial transfer status flag (b5 of address 001a 16 ) of serial i/o1 control register 2 indicates the shift register status of serial i/o1, and is set to ? by writing into the serial i/o1 register, which be- comes a transfer start trigger and reset to ??after completion of 8-bit transfer. at the same time, a serial i/o1 interrupt request oc- curs. when the external synchronous clock is selected, the contents of the serial i/o1 register are continuously shifted while transfer clocks are input to s clk1 . therefore, the clock needs to be con- trolled externally. (3) automatic transfer serial i/o mode the serial i/o1 automatic transfer controller controls the write and read operations of the serial i/o1 register, so that the function of address 001b 16 is used as a transfer counter (1-byte unit). when performing serial transfer through the serial i/o automatic transfer ram (addresses 0f00 16 to 0fff 16 ), it is necessary to set the serial i/o1 automatic transfer data pointer (address 0018 16 ) beforehand. input the low-order 8 bits of the first data store address to be seri- ally transferred to the automatic transfer data pointer set bits. when the internal synchronous clock is selected, the transfer in- terval for each 1-byte data can be set by the automatic transfer interval set bits (b0 to b4 of address 001c 16 ) of serial i/o1 control register 3 in the following cases: 1. when using no handshake signal 2. when using the s rdy1 output, s busy1 output, and s stb1 output of the handshake signal independently 3. when using a combination of s rdy1 output and s stb1 output or a combination of s busy1 output and s stb1 output of the hand- shake signal. it is possible to select one of 32 different values, namely 2 to 33 cycles of the transfer clock, as a setting value. when using the s busy1 output and selecting the s busy1 output s stb1 output function selection bit (b4 of address 001a 16 ) of serial i/o1 control register 2 as the signal for all transfer data, provided that the automatic transfer interval setting is valid, a transfer inter- val is placed before the start of transmission/reception of the first data and after the end of transmission/reception of the last data. for s stb1 output, regardless of the contents of the s busy1 output ?s stb1 output function selection bit (b4), the transfer interval for each 1-byte data is longer than the set value by 2 cycles. furthermore, when using a combination of s busy1 output and s stb1 output as a signal for all transfer data, the transfer interval after the end of transmission/reception of the last data is longer than the set value by 2 cycles. when the external synchronous clock is selected, automatic trans- fer interval setting is disabled. after completion of the above bit setup, if the internal synchronous clock is selected, automatic serial transfer is started by writing the value of ?umber of transfer bytes ?1?into the transfer counter (address 001b 16 ). when the external synchronous clock is selected, write the value of ?umber of transfer bytes ?1?into the transfer counter and keep an internal system clock interval of 5 cycles or more. after that, input transfer clock to s clk1 . as a transfer interval for each 1-byte data transfer, keep an inter- nal system clock interval of 5 cycles or more from the clock rise time of the last bit. regardless of whether the internal or external synchronous clock is selected, the automatic transfer data pointer and the transfer counter are decremented after each 1-byte data is received and then written into the automatic transfer ram. the serial transfer status flag (b5 of address 001a 16 ) is set to ??by writing data into the transfer counter. writing data becomes a transfer start trigger, and the serial transfer status flag is reset to ??after the last data is written into the automatic transfer ram. at the same time, a se- rial i/o1 interrupt request occurs. the values written in the automatic transfer data pointer set bits (b0 to b7 of address 0018 16 ) and the automatic transfer interval set bits (b0 to b4 of address 001c 16 ) are held in the latch. when data is written into the transfer counter, the values latched in the automatic transfer data pointer set bits (b0 to b7) and the automatic transfer interval set bits (b0 to b4) are transferred to the decrement counter. fig. 24 structure of serial i/o1 automatic transfer data pointer b 7b 0 s e r i a l i / o 1 a u t o m a t i c t r a n s f e r d a t a p o i n t e r ( s i o 1 d p : a d d r e s s 0 0 1 8 1 6 ) a u t o m a t i c t r a n s f e r d a t a p o i n t e r s e t b i t s s p e c i f y t h e l o w - o r d e r 8 b i t s o f t h e f i r s t d a t a s t o r e a d d r e s s o n t h e s e r i a l i / o a u t o m a t i c t r a n s f e r r a m . d a t a i s w r i t t e n i n t o t h e l a t c h a n d r e a d f r o m t h e d e c r e m e n t c o u n t e r .
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 32 fig. 25 automatic transfer serial i/o operation f f f 1 6 a u t o m a t i c t r a n s f e r r a m t r a n s f e r c o u n t e r a u t o m a t i c t r a n s f e r d a t a p o i n t e r s e r i a l i / o 1 r e g i s t e r f 5 2 1 6 f 5 1 1 6 f 5 0 1 6 f 4 f 1 6 f 4 e 1 6 f 0 0 1 6 0 4 1 6 5 2 1 6 s i n 1 s o u t 1
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 33 fig. 27 s busy1 input operation (internal synchronous clock) fig. 28 s busy1 input operation (external synchronous clock) (4) handshake signal 1. s stb1 output signal the s stb1 output is a signal to inform an end of transmission/re- ception to the serial transfer destination . the s stb1 output signal can be used only when the internal synchronous clock is selected. in the initial status, namely, in the status in which the serial i/o ini- tialization bit (b4) is reset to 0 , the s stb1 output goes to l , or the s stb1 output goes to h . at the end of transmit/receive operation, when the data of the se- rial i/o1 register is all output from s out1 , pulses are output in the period of 1 cycle of the transfer clock so as to cause the s stb1 output to go h or the s stb1 output to go l . after that, each pulse is returned to the initial status in which s stb1 output goes to l or the s stb1 output goes to h . furthermore, after 1 cycle, the serial transfer status flag (b5) is re- set to 0 . in the automatic transfer serial i/o mode, whether the s stb1 out- put is to be active at an end of each 1-byte data or after completion of transfer of all data can be selected by the s busy1 output s stb1 output function selection bit (b4 of address 001a 16 ) of serial i/o1 control register 2. 2. s busy1 input signal the s busy1 input is a signal which receives a request for a stop of transmission/reception from the serial transfer destination. when the internal synchronous clock is selected, input an h level signal into the s busy1 input and an l level signal into the s busy1 input in the initial status in which transfer is stopped. when starting a transmit/receive operation, input an l level sig- nal into the s busy1 input and an h level signal into the s busy1 input in the period of 1.5 cycles or more of the transfer clock. then, transfer clocks are output from the s clk1 output. when an h level signal is input into the s busy1 input and an l level signal into the s busy1 input after a transmit/receive opera- tion is started, this transmit/receive operation are not stopped immediately and the transfer clocks from the s clk1 output is not stopped until the specified number of bits are transmitted and re- ceived. the handshake unit of the 8-bit serial i/o is 8 bits and that of the automatic transfer serial i/o is 8 bits. when the external synchronous clock is selected, input an h level signal into the s busy1 input and an l level signal into the s busy1 input in the initial status in which transfer is stopped. at this time, the transfer clocks to be input in s clk1 become invalid. during serial transfer, the transfer clocks to be input in s clk1 be- come valid, enabling a transmit/receive operation, while an l level signal is input into the s busy1 input and an h level signal is input into the s busy1 input. when changing the input values in the s busy1 input and the s busy1 input at these operations, change them when the s clk1 input is in a high state. when the high impedance of the s out1 output is selected by the s out1 pin control bit (b6), the s out1 output becomes active, en- abling serial transfer by inputting a transfer clock to s clk1 , while an l level signal is input into the s busy1 input and an h level signal is input into the s busy1 input. fig. 26 s stb1 output operation s stb1 s clk1 s out1 serial transfer status flag s busy1 s clk1 s out1 s busy1 s clk1 s out1 invalid (output high-impedance) 3. s busy1 output signal the s busy1 output is a signal which requests a stop of transmis- sion/reception to the serial transfer destination. in the automatic transfer serial i/o mode, regardless of the internal or external syn- chronous clock, whether the s busy1 output is to be active at transfer of each 1-byte data or during transfer of all data can be selected by the s busy1 output s stb1 output function selection bit (b4). in the initial status, the status in which the serial i/o initialization bit (b4) is reset to 0 , the s busy1 output goes to h and the s busy1 output goes to l .
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 34 when the internal synchronous clock is selected, in the 8-bit serial i/o mode and the automatic transfer serial i/o mode (s busy1 out- put function outputs in 1-byte units), the s busy1 output goes to l and the s busy1 output goes to h before 0.5 cycle (transfer clock) of the timing at which the transfer clock from the s clk1 output goes to l at a start of transmit/receive operation. in the automatic transfer serial i/o mode (the s busy1 output func- tion outputs all transfer data), the s busy1 output goes to l and the s busy1 output goes to h when the first transmit data is writ- ten into the serial i/o1 register (address 001b 16 ). when the external synchronous clock is selected, the s busy1 out- put goes to l and the s busy1 output goes to h when transmit data is written into the serial i/o1 register to start a transmit opera- tion, regardless of the serial i/o transfer mode. at termination of transmit/receive operation, the s busy1 output re- turns to h and the s busy1 output returns to l , the initial status, when the serial transfer status flag is set to 0 , regardless of whether the internal or external synchronous clock is selected. furthermore, in the automatic transfer serial i/o mode (s busy1 output function outputs in 1-byte units), the s busy1 output goes to h and the s busy1 output goes to l each time 1-byte of receive data is written into the automatic transfer ram. fig. 29 s busy1 output operation (internal synchronous clock, 8-bit serial i/o) fig. 30 s busy1 output operation (external synchronous clock, 8-bit serial i/o) fig. 31 s busy1 output operation in automatic transfer serial i/o mode (internal synchronous clock, s busy1 output function outputs each 1-byte) s busy1 s clk1 s out1 serial transfer status flag serial transfer status flag s busy1 s clk1 write to serial i/o1 register s clk1 s busy1 s out1 automatic transfer interval serial transfer status flag automatic transfer ram serial i/o1 register serial i/o1 register automatic transfer ram
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 35 4. s rdy1 output signal the s rdy1 output is a transmit/receive enable signal which in- forms the serial transfer destination that transmit/receive is ready. in the initial status, when the serial i/o initialization bit (b4) is reset to 0 , the s rdy1 output goes to l and the s rdy1 output goes to h . after transmitted data is stored in the serial i/o1 register (ad- dress 001b 16 ) and a transmit/receive operation becomes ready, the s rdy1 output goes to h and the s rdy1 output goes to l . when a transmit/receive operation is started and the transfer clock goes to l , the s rdy1 output goes to l and the s rdy1 output goes to h . 5. s rdy1 input signal the s rdy1 input signal becomes valid only when the s rdy1 input and the s busy1 output are used. the s rdy1 input is a signal for receiving a transmit/receive ready completion signal from the se- rial transfer destination. when the internal synchronous clock is selected, input a low level signal into the s rdy1 input and a high level signal into the s rdy1 input in the initial status in which the transfer is stopped. when an h level signal is input into the s rdy1 input and an l level signal is input into the s rdy1 input for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the s clk1 output and a transmit/receive operation is started. after the transmit/receive operation is started and an l level sig- nal is input into the s rdy1 input and an h level signal into the s rdy1 input, this operation cannot be immediately stopped. after the specified number of bits are transmitted and received, the transfer clocks from the s clk1 output is stopped. the hand- shake unit of the 8-bit serial i/o and that of the automatic transfer serial i/o are of 8 bits. when the external synchronous clock is selected, the s rdy1 input becomes one of the triggers to output the s busy1 signal. to start a transmit/receive operation (s busy1 output: l , s busy1 output: h ), input an h level signal into the s rdy1 input and an l level signal into the s rdy1 input, and also write transmit data into the serial i/o1 register. fig. 32 s rdy1 output operation fig. 33 s rdy1 input operation (internal synchronous clock) s rdy1 s clk1 write to serial i/o1 register s rdy1 s clk1 s out1
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 36 fig. 34 handshake operation at serial i/o1 mutual connecting (1) fig. 35 handshake operation at serial i/o1 mutual connecting (2) a: b: s clk1 s rdy1 s busy1 s busy1 s rdy1 s clk1 a: b: write to serial i/o1 register s clk1 s rdy1 s busy1 internal synchronous clock selection external synchronous clock selection write to serial i/o1 register a: b: s clk1 s rdy1 s busy1 s busy1 s rdy1 s clk1 a: b: write to serial i/o1 register s clk1 s rdy1 s busy1 internal synchronous clock selection external synchronous clock selection write to serial i/o1 register
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 37 serial i/o2 serial i/o2 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation during serial i/o2 opera- tion. (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode can be selected by setting the serial i/o2 mode selection bit (b6) of the serial i/o2 control fig. 37 operation of clock synchronous serial i/o2 function fig. 36 block diagram of clock synchronous serial i/o2 register (address 001d 16 ) to 1 . for clock synchronous serial i/o, the transmitter and the receiver must use the same clock for serial i/o2 operation. if an internal clock is used, transmit/receive is started by a write signal to the serial i/o2 transmit/receive buffer register (tb/rb) (address 001f 16 ). when p6 7 (s clk22 ) is selected as a clock i/o pin, s rdy2 output function is invalid, and p6 6 (s clk21 ) is used as an i/o port. 1 / 4 1 / 4 f / f p 6 6 / s c l k 2 1 p 6 4 / r x d p 6 5 / t x d p 6 7 / s r d y 2 / s c l k 2 2 0 1 0 1 x i n 1 / 2 x c i n 1 0 p 6 7 / s r d y 2 / s c l k 2 2 s e r i a l i / o 2 s t a t u s r e g i s t e r s e r i a l i / o 2 c o n t r o l r e g i s t e r r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 f 1 6 r e c e i v e s h i f t r e g i s t e r r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) c l o c k c o n t r o l c i r c u i t s h i f t c l o c k s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t b a u d r a t e g e n e r a t o r d i v i s i o n r a t i o 1 / ( n + 1 ) a d d r e s s 0 0 3 7 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t f a l l i n g e d g e d e t e c t o r t r a n s m i t b u f f e r r e g i s t e r d a t a b u s a d d r e s s 0 0 1 f 1 6 s h i f t c l o c k t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t a d d r e s s 0 0 1 e 1 6 d a t a b u s a d d r e s s 0 0 1 d 1 6 t r a n s m i t s h i f t r e g i s t e r s e r i a l i / o 2 c l o c k i / o p i n s e l e c t i o n b i t i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t b r g c l o c k s w i t c h b i t s e r i a l i / o 2 c l o c k i / o p i n s e l e c t i o n b i t d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transmit/receive shift clock (1/2 to 1/2048 of internal clock or external clock) serial i/o2 output txd serial i/o2 input rxd write-in signal to serial i/o2 transmit/receive buffer register (address 001f 16 ) overrun error (oe) detection notes 1 : the transmit interrupt (ti) can be selected to occur either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting transmit interrupt source selection bit (tic) of the serial i/o2 control register. 2 : if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3 : the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes 1 . receive enable signal s rdy2
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 38 (2) asynchronous serial i/o (uart) mode the asynchronous serial i/o (uart) mode can be selected by clearing the serial i/o2 mode selection bit (b6) of the serial i/o2 control register (address 001d 16 ) to 0 . eight serial data transfer formats can be selected and the transfer formats used by the transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer (the two buffers have the same address in memory). since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the re- ceive buffer. the transmit buffer can also hold the next data to be transmitted, and the receive buffer can receive 2-byte data con- tinuously. fig. 39 operation of uart serial i/o2 function fig. 38 block diagram of uart serial i/o2 o e p e f e 1 / 1 6 1 / 1 6 t r a n s m i t b u f f e r r e g i s t e r c l o c k c o n t r o l c i r c u i t p 6 6 / s c l k 2 1 p 6 4 / r x d p 6 5 / t x d p 6 7 / s r d y 2 / s c l k 2 2 0 1 1 / 4 0 1 x i n 1 / 2 x c i n 1 d a t a b u s r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 f 1 6 r e c e i v e s h i f t r e g i s t e r r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) b a u d r a t e g e n e r a t o r d i v i s i o n r a t i o 1 / ( n + 1 ) a d d r e s s 0 0 3 7 1 6 s t / s p / p a g e n e r a t o r d a t a b u s t r a n s m i t s h i f t r e g i s t e r a d d r e s s 0 0 1 f 1 6 t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) a d d r e s s 0 0 1 e 1 6 s t d e t e c t o r u a r t c o n t r o l r e g i s t e r a d d r e s s 0 0 3 8 1 6 c h a r a c t e r l e n g t h s e l e c t i o n b i t a d d r e s s 0 0 1 d 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t 8 b i t s e r i a l i / o 2 c o n t r o l r e g i s t e r s e r i a l i / o 2 s t a t u s r e g i s t e r s p d e t e c t o r s e r i a l i / o 2 c l o c k i / o p i n s e l e c t i o n b i t i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t b r g c l o c k s w i t c h b i t tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1* st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock * generated at 2nd bit in 2-stop bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit serial i/o2 input r x d write-in signal to transmit buffer register serial i/o2 output t x d read-out signal from receive buffer register
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 39 [serial i/o2 control register] sio2con (001d 16 ) the serial i/o2 control register contains eight control bits for serial i/o2 functions. [uart control register] uartcon (0038 16 ) this is a 7 bit register containing four control bits, of which four bits are valid when uart is selected, and of which three bits are always valid. data format of serial data receive/transfer and the output structure of the p6 5 /txd pin and others are set by this register. [serial i/o2 status register] sio2sts (001e 16 ) the read-only serial i/o2 status register consists of seven flags (b0 to b6) which indicate the operating status of the serial i/o2 function and various errors. three of the flags (b4 to b6) are only valid in the uart mode. the receive buffer full flag (b1) is cleared to 0 when the receive buffer is read. the error detection is performed at the same time data is trans- ferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. a writing to the serial i/o2 status register clears error flags oe, pe, fe, and se (b3 to b6, re- spectively). writing 0 to the serial i/o2 enable bit (sioe : b7 of the serial i/o2 control register) also clears all the status flags, in- cluding the error flags. all bits of the serial i/o2 status register are initialized to 0 at re- set, but if the transmit enable bit (b4) of the serial i/o2 control register has been set to 1 , the transmit shift register shift comple- tion flag (b2) and the transmit buffer empty flag (b0) become 1 . [serial i/o2 transmit buffer register/receive buffer register] tb/rb (001f 16 ) the transmit buffer and the receive buffer are located in the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0 . [baud rate generator] brg (0037 16 ) the baud rate generator determines the baud rate for serial trans- fer. with the 8-bit counter having a reload register, the baud rate generator divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator.
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 40 fig. 40 structure of serial i/o2 related register b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift register shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns 1 when read) serial i/o2 status register (sio2sts : address 001e 16 ) serial i/o2 control register (sio2con : address 001d 16 ) b0 b0 b7 uart control register (uartcon : address 0038 16 ) character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p6 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) brg clock switch bit 0: x in or x cin (depends on internal system clock) 1: x cin serial i/o2 clock i/o pin selection bit 0: s clk21 (p6 7 /s clk22 pin is used as i/o port or s rdy2 output pin.) 1: s clk22 (p6 6 /s clk21 pin is used as i/o port.) not used (return 1 when read) b0 brg count source selection bit (css) 0: f(x in ) or f(x cin )/2 or f(x cin ) 1: f(x in )/4 or f(x cin )/8 or f(x cin )/4 serial i/o2 synchronous clock selection bit (scs) 0: brg/ 4 (when clock synchronous serial i/o is selected) brg/16 (uart is selected) 1: external clock input (when clock synchronous serial i/o is selected) external clock input/16 (uart is selected) s rdy2 output enable bit (srdy) 0: p6 7 pin operates as ordinary i/o pin 1: p6 7 pin operates as s rdy2 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o2 mode selection bit (siom) 0: asynchronous serial i/o (uart) 1: clock synchronous serial i/o serial i/o2 enable bit (sioe) 0: serial i/o2 disabled (pins p6 4 to p6 7 operate as ordinary i/o pins) 1: serial i/o2 enabled (pins p6 4 to p6 7 operate as serial i/o pins)
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 41 serial i/o3 the serial i/o3 function can be used only for 8-bit clock synchro- nous serial i/o. all serial i/o pins are shared with port p9, which can be set with the serial i/o3 control register (address 0eec 16 ). [serial i/o3 control register (sio3con)] 0eec 16 the serial i/o3 control register contains eight bits which control various serial i/o functions. either the internal clock or external clock can be selected as syn- chronous clock for serial i/o3 transfer. the internal clock can use a built-in dedicated divider where 6 dif- ferent clocks are selected. in the case of the internal clock used, transfer is started by a write signal to the serial i/o3 register (ad- dress 0eed 16 ). when 8-bit data has been transferred, the s out3 pin goes to high impedance state. in the case of the external clock used, the clock must be externally controlled. it is because the contents of serial i/o3 register is kept shifted while the clock is being input. additionally, the function to put the s out3 pin high impedance state at completion of data transfer is not available. the serial i/o3 interrupt request bit is set at completion of 8-bit data transfer, regardless of use of the internal clock or external clock. fig. 42 structure of serial i/o3 control register fig. 41 block diagram of serial i/o3 1 0 0 1 0 1 s r d y 3 s c l k 3 0 1 1 / 4 1 / 8 1 / 1 6 1 / 3 2 1 / 6 4 1 / 1 2 8 d a t a b u s s e r i a l i / o 3 i n t e r r u p t r e q u e s t s e r i a l i / o 3 p o r t s e l e c t i o n b i t s e r i a l i / o 3 c o u n t e r ( 3 ) s e r i a l i / o 3 s h i f t r e g i s t e r ( 8 ) s y n c h r o n i z a t i o n c i r c u i t s e r i a l i / o 3 p o r t s e l e c t i o n b i t s e r i a l i / o 3 s y n c h r o n o u s c l o c k s e l e c t i o n b i t s r d y 3 o u t p u t s e l e c t i o n b i t e x t e r n a l c l o c k i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s d i v i d e r p 9 2 / s c l k 3 p 9 1 / s o u t 3 p 9 0 / s i n 3 p 9 2 l a t c h p 9 1 l a t c h p 9 3 l a t c h p 9 3 / s r d y 3 x c i n 1 / 2 x i n 0 1 i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t s e r i a l i / o 3 c o n t r o l r e g i s t e r ( s i o 3 c o n : a d d r e s s 0 e e c 1 6 ) b 7 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s 0 0 0 : f ( x i n ) / 4 ( f ( x c i n ) / 8 ) 0 0 1 : f ( x i n ) / 8 ( f ( x c i n ) / 1 6 ) 0 1 0 : f ( x i n ) / 1 6 ( f ( x c i n ) / 3 2 ) 0 1 1 : f ( x i n ) / 3 2 ( f ( x c i n ) / 6 4 ) 1 1 0 : f ( x i n ) / 6 4 ( f ( x c i n ) / 1 2 8 ) 1 1 1 : f ( x i n ) / 1 2 8 ( f ( x c i n ) / 2 5 6 ) s e r i a l i / o 3 p o r t s e l e c t i o n b i t ( p 9 1 , p 9 2 ) 0 : i / o p o r t 1 : s o u t 3 , s c l k 3 s i g n a l o u t p u t s r d y 3 o u t p u t s e l e c t i o n b i t ( p 9 3 ) 0 : i / o p o r t 1 : s r d y 3 s i g n a l o u t p u t t r a n s f e r d i r e c t i o n s e l e c t i o n b i t 0 : l s b f i r s t 1 : m s b f i r s t s e r i a l i / o 3 s y n c h r o n o u s c l o c k s e l e c t i o n b i t 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k p 9 1 / s o u t 3 p - c h a n n e l o u t p u t d i s a b l e b i t ( p 9 1 ) 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n d r a i n o u t p u t ( i n o u t p u t m o d e ) b 0 b 2 b 1 b 0
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 42 fig. 43 timing of serial i/o3 (lsb first) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t r a n s f e r c l o c k s e r i a l i / o 3 o u t p u t s o u t 3 s e r i a l i / o 3 i n p u t s i n 3 r e c e i v e e n a b l e s i g n a l s r d y 3 s e r i a l i / o 3 r e g i s t e r w r i t e s i g n a l s e r i a l i / o 3 i n t e r r u p t r e q u e s t b i t s e t n o t e: w h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e t r a n s f e r c l o c k , t h e s o u t 3 p i n g o e s t o h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n . s y n c h r o n o u s c l o c k ( n o t e )
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 43 fld controller the M38B7 group has fluorescent display (fld) drive and control circuits. table 9 shows the fld controller specifications. specifications ?52 pins (20 pins can be switched to general-purpose ports) ?4 pins (all 4 pins can be switched to general-purpose ports) (a driver ic must be installed externally) ?used fld output 28 segment ? 28 digit (segment number + digit number 56) ?used digit output 40 segment ? 16 digit (segment number 40, digit number 16) ?connected to m35501 56 segment ? (connected number of m35501) digit (segment number 56, digit number number of m35501 ? 16) ?used p6 4 to p6 7 expansion 52 segment ? 16 digit (segment number 52, digit number 16) ?4.0 s to 1024 s (count source x in /16, 4 mhz) ?16.0 s to 4096 s (count source x in /64, 4 mhz) ?4.0 s to 1024 s (count source x in /16, 4 mhz) ?16.0 s to 4096 s (count source x in /64, 4 mhz) ?digit interrupt ?fld blanking interrupt ?key-scan using digit ?key-scan using segment ?digit pulse output function this function automatically outputs digit pulses. ?m35501 connection function the number of digits can be increased easily by using the output of dim out (p7 3 ) as clk for the m35501. ?toff section generating/nothing function this function does not generate toff1 section when the connected outputs are the same. ?gradation display function this function allows each segment to be set for dark or bright display. ?p6 4 to p6 7 expansion function this function provides 16 lines of digit outputs from four ports by attaching the decoder converting 4-bit data to 16-bit data. item fld controller port high-breakdown- voltage output port cmos port display pixel number period dimmer time interrupt key-scan expanded function table 9 fld controller specifications
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 44 fig. 44 block diagram of fld control circuit p 2 0 / f l d 0 d i g / f l d 0 e f 3 1 6 0 0 0 4 1 6 8 p 2 1 / f l d 1 d i g / f l d p 2 2 / f l d 2 d i g / f l d p 2 3 / f l d 3 d i g / f l d p 2 4 / f l d 4 d i g / f l d p 2 5 / f l d 5 d i g / f l d p 2 6 / f l d 6 d i g / f l d p 2 7 / f l d 7 d i g / f l d 0 0 0 2 1 6 8 p 1 0 / f l d 1 6 p 1 1 / f l d 1 7 p 1 2 / f l d 1 8 p 1 3 / f l d 1 9 p 1 4 / f l d 2 0 p 1 5 / f l d 2 1 p 1 6 / f l d 2 2 p 1 7 / f l d 2 3 0 0 0 6 1 6 8 p 3 0 / f l d 2 4 p 3 1 / f l d 2 5 p 3 2 / f l d 2 6 p 3 3 / f l d 2 7 p 3 4 / f l d 2 8 p 3 5 / f l d 2 9 p 3 6 / f l d 3 0 p 3 7 / f l d 3 1 0 0 0 8 1 6 0 e f 9 1 6 8 p 4 0 / f l d 3 2 p 4 1 / f l d 3 3 p 4 2 / f l d 3 4 p 4 3 / f l d 3 5 p 4 4 / f l d 3 6 p 4 5 / f l d 3 7 p 4 6 / f l d 3 8 p 4 7 / f l d 3 9 f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p 0 e 0 0 1 6 0 e d f 1 6 p 0 0 / f l d 8 d i g / f l d 0 e f 2 1 6 0 0 0 0 1 6 8 p 0 1 / f l d 9 d i g / f l d p 0 2 / f l d 1 0 d i g / f l d p 0 3 / f l d 1 1 d i g / f l d p 0 4 / f l d 1 2 d i g / f l d p 0 5 / f l d 1 3 d i g / f l d p 0 6 / f l d 1 4 d i g / f l d p 0 7 / f l d 1 5 d i g / f l d 0 0 0 a 1 6 0 e f a 1 6 8 p 5 0 / f l d 4 0 p 5 1 / f l d 4 1 p 5 2 / f l d 4 2 p 5 3 / f l d 4 3 p 5 4 / f l d 4 4 p 5 5 / f l d 4 5 p 5 6 / f l d 4 6 p 5 7 / f l d 4 7 f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p 0 0 0 c 1 6 0 e f b 1 6 8 p 6 0 / f l d 4 8 p 6 1 / f l d 4 9 p 6 2 / f l d 5 0 p 6 3 / f l d 5 1 p 6 4 / f l d 5 2 p 6 5 / f l d 5 3 p 6 6 / f l d 5 4 p 6 7 / f l d 5 5 f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p m a i n a d d r e s s b u s l o c a l a d d r e s s b u s f l d a u t o m a t i c d i s p l a y r a m m a i n d a t a b u s l o c a l d a t a b u s f l d b l a n k i n g i n t e r r u p t f l d d i g i t i n t e r r u p t f l d c m o d e r e g i s t e r ( 0 e f 4 1 6 ) f l d d a t a p o i n t e r r e l o a d r e g i s t e r ( 0 e f 8 1 6 ) f l d d a t a p o i n t e r ( 0 e f 8 1 6 ) t i m i n g g e n e r a t o r a d d r e s s d e c o d e r d i g i t o u t p u t s e t s w i t c h r e g i s t e r f l d / p o r t s w i t c h r e g i s t e r
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 45 fig. 45 structure of fldc related registers (1) b 7b 6b 5b 4b3 b 2b 1b0 f l d c m o d e r e g i s t e r ( f l d m : a d d r e s s 0 e f 4 1 6 ) a u t o m a t i c d i s p l a y c o n t r o l b i t 0 : g e n e r a l - p u r p o s e m o d e 1 : a u t o m a t i c d i s p l a y m o d e d i s p l a y s t a r t b i t 0 : s t o p d i s p l a y 1 : d i s p l a y ( s t a r t t o d i s p l a y b y s w i t c h i n g 0 t o 1 ) t s c a n c o n t r o l b i t s b 3 b 2 0 0 : f l d d i g i t i n t e r r u p t ( a t r i s i n g e d g e o f e a c h d i g i t ) 0 1 : 1 ? t d i s p 1 0 : 2 ? t d i s pf l d b l a n k i n g i n t e r r u p t 1 1 : 3 ? t d i s p( a t f a l l i n g e d g e o f t h e l a s t d i g i t ) t i m i n g n u m b e r c o n t r o l b i t 0 : 1 6 t i m i n g m o d e 1 : 3 2 t i m i n g m o d e g r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t 0 : n o t s e l e c t i n g 1 : s e l e c t i n g ( n o t e ) t d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 1 6 1 : f ( x i n ) / 6 4 h i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t i o n b i t 0 : d r i v a b i l i t y s t r o n g 1 : d r i v a b i l i t y w e a k n o t e : w h e n t h e g r a d a t i o n d i s p l a y m o d e i s s e l e c t e d , t h e m a x . n u m b e r o f t i m i n g i s 1 6 t i m i n g . ( b e s u r e t o s e t t h e t i m i n g n u m b e r c o n t r o l b i t t o 0 . ) b 7b 6b 5b 4b3 b 2b 1b0 f l d o u t p u t c o n t r o l r e g i s t e r ( f l d c o n : a d d r e s s 0 e f c 1 6 ) p 6 4 t o p 6 7 o u t p u t r e v e r s e b i t 0 : o u t p u t n o r m a l l y 1 : r e v e r s e o u t p u t n o t u s e d ( r e t u r n 0 w h e n r e a d ) ; ( d o n o t w r i t e 1 . ) p 6 4 t o p 6 7 t o f f i n v a l i d b i t 0 : o p e r a t i o n n o r m a l l y 1 : t o f f i n v a l i d n o t u s e d ( r e t u r n 0 w h e n r e a d ) ; ( d o n o t w r i t e 1 . ) p 7 3 d i m m e r o u t p u t c o n t r o l b i t 0 : n o r m a l p o r t 1 : d i m m e r o u t p u t g e n e r a t i n g / n o t o f c m o s p o r t t o f f s e c t i o n s e l e c t i o n b i t 0 : t o f f s e c t i o n n o t g e n e r a t e d 1 : t o f f s e c t i o n g e n e r a t e d g e n e r a t i n g / n o t o f h i g h - b r e a k d o w n v o l t a g e p o r t t o f f s e c t i o n s e l e c t i o n b i t 0 : t o f f s e c t i o n n o t g e n e r a t e d 1 : t o f f s e c t i o n g e n e r a t e d t o f f 2 s e t / r e s e t s w i t c h b i t 0 : t o f f 2 r e s e t ; t o f f 1 s e t 1 : t o f f 2 s e t ; t d i s p r e s e t
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 46 fig. 46 structure of fldc related registers (2) b 7b 6b 5b 4b 3b 2b 1 b 0 p o r t p 4 f l d / p o r t s w i t c h r e g i s t e r ( p 4 f p r : a d d r e s s 0 e f 9 1 6 ) p o r t p 4 0 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 1 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 2 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 3 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 4 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 5 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 6 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 7 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 5 f l d / p o r t s w i t c h r e g i s t e r ( p 5 f p r : a d d r e s s 0 e f a 1 6 ) b 7b 6b 5b 4b 3b 2b 1 b 0 p o r t p 5 0 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 5 1 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 5 2 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 5 3 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 5 4 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 5 5 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 5 6 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 5 7 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 47 fig. 47 structure of fldc related registers (3) b 7b 6b 5b 4b 3 b 2 b 1b 0 p o r t p 6 f l d / p o r t s w i t c h r e g i s t e r ( p 6 f p r : a d d r e s s 0 e f b 1 6 ) p o r t p 6 0 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 6 1 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 6 2 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 6 3 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 6 4 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 6 5 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 6 6 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 6 7 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 48 fig. 48 structure of fldc related registers (4) b 7b 6b 5b 4b 3b 2 b 1b 0 p o r t p 0 d i g i t o u t p u t s e t s w i t c h r e g i s t e r ( p 0 d o r : a d d r e s s 0 e f 2 1 6 ) p o r t p 0 0 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 0 1 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 0 2 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 0 3 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 0 4 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 0 5 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 0 6 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 0 7 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t b 7b 6b 5b 4b 3b 2 b 1b 0 p o r t p 2 d i g i t o u t p u t s e t s w i t c h r e g i s t e r ( p 2 d o r : a d d r e s s 0 e f 3 1 6 ) p o r t p 2 0 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 2 1 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 2 2 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 2 3 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 2 4 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 2 5 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 2 6 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 2 7 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 49 fig. 49 segment/digit setting example fld automatic display pins p0 to p6 are the pins capable of automatic display output for the fld. the fld starts operating by setting the automatic display control bit (bit 0 at address 0ef4 16 ) to 1 . there is the fld output function that outputs the ram contents from the port every timing or the digit output function that drives the port high with a digit tim- setting method the individual bits of the digit output set switch registers (addresses 0ef2 16 , 0ef3 16 ) can set each pin to either an fld port ( 0 ) or a digit port ( 1 ). when the pins are set for the digit port, the digit pulse output function is enabled, so that the digit pulses can always be output regardless the value of fld automatic display ram. setting the automatic display control bit (bit 0 of address 0ef4 16 ) to 1 can set these ports to the fld exclusive use port. the individual bits of the fld/port switch register (addresses 0ef9 16 to 0efb 16 ) can set each pin to either an fld port ( 1 ) or a general-purpose port ( 0 ). the individual bits of the port p6 fld/port switch register (address 0efb 16 ) can set each pin to either fld port ( 1 ) or general-purpose port ( 0 ). a variety of output pulses can be available by setting of the fld output control register (address 0efc 16 ). the port output structure is the cmos output. when using the port as a display pin, a driver ic must be in- stalled externally. ing. the fld can be displayed using the fld output for the seg- ments and the digit or fld output for the digits. when using the fld output for the digits, be sure to write digit display patterns to the ram in advance. the remaining segment and digit lines can be used as general-purpose ports. settings of each port are shown below. table 10 pins in fld automatic display mode port p0, p2 automatic display pin fld 0 to fld 15 p1, p3 fld 16 to fld 31 p4, p5, p6 0 to p6 3 p6 4 to p6 7 fld 32 to fld 51 fld 52 to fld 55 p o r t p 0 p o r t p 1 n u m b e r o f s e g m e n t s n u m b e r o f d i g i t s p o r t p 2 3 6 1 6 p o r t p 3 s e t t i n g e x a m p l e 1 t h i s i s a r e g i s t e r s e t u p e x a m p l e w h e r e o n l y f l d o u t p u t i s u s e d . i n t h i s c a s e , t h e d i g i t d i s p l a y o u t p u t p a t t e r n m u s t b e s e t i n t h e f l d a u t o m a t i c d i s p l a y r a m i n a d v a n c e . 1 1 1 1 1 1 1 1 f l d 3 2 ( s e g o u t p u t ) f l d 3 3 ( s e g o u t p u t ) f l d 3 4 ( s e g o u t p u t ) f l d 3 5 ( s e g o u t p u t ) f l d 3 6 ( s e g o u t p u t ) f l d 3 7 ( s e g o u t p u t ) f l d 3 8 ( s e g o u t p u t ) f l d 3 9 ( s e g o u t p u t ) f l d 1 6 ( s e g o u t p u t ) f l d 1 7 ( s e g o u t p u t ) f l d 1 8 ( s e g o u t p u t ) f l d 1 9 ( s e g o u t p u t ) f l d 2 0 ( s e g o u t p u t ) f l d 2 1 ( s e g o u t p u t ) f l d 2 2 ( s e g o u t p u t ) f l d 2 3 ( s e g o u t p u t ) f l d 0 ( d i g o u t p u t ) f l d 1 ( d i g o u t p u t ) f l d 2 ( d i g o u t p u t ) f l d 3 ( d i g o u t p u t ) f l d 4 ( d i g o u t p u t ) f l d 5 ( d i g o u t p u t ) f l d 6 ( d i g o u t p u t ) f l d 7 ( d i g o u t p u t ) 0 0 0 0 0 0 0 0 f l d 8 ( d i g o u t p u t ) f l d 9 ( d i g o u t p u t ) f l d 1 0 ( d i g o u t p u t ) f l d 1 1 ( d i g o u t p u t ) f l d 1 2 ( d i g o u t p u t ) f l d 1 3 ( d i g o u t p u t ) f l d 1 4 ( d i g o u t p u t ) f l d 1 5 ( d i g o u t p u t ) 0 0 0 0 0 0 0 0 f l d 2 4 ( s e g o u t p u t ) f l d 2 5 ( s e g o u t p u t ) f l d 2 6 ( s e g o u t p u t ) f l d 2 7 ( s e g o u t p u t ) f l d 2 8 ( s e g o u t p u t ) f l d 2 9 ( s e g o u t p u t ) f l d 3 0 ( s e g o u t p u t ) f l d 3 1 ( s e g o u t p u t ) p o r t p 4 1 1 1 1 1 1 1 1 f l d 4 0 ( s e g o u t p u t ) f l d 4 1 ( s e g o u t p u t ) f l d 4 2 ( s e g o u t p u t ) f l d 4 3 ( s e g o u t p u t ) f l d 4 4 ( s e g o u t p u t ) f l d 4 5 ( s e g o u t p u t ) f l d 4 6 ( s e g o u t p u t ) f l d 4 7 ( s e g o u t p u t ) p o r t p 5 1 1 1 1 0 0 0 0 f l d 4 8 ( s e g o u t p u t ) f l d 4 9 ( s e g o u t p u t ) f l d 5 0 ( s e g o u t p u t ) f l d 5 1 ( s e g o u t p u t ) f l d 5 2 ( p o r t o u t p u t ) f l d 5 3 ( p o r t o u t p u t ) f l d 5 4 ( p o r t o u t p u t ) f l d 5 5 ( p o r t o u t p u t ) p o r t p 6 p o r t p 0 p o r t p 1 p o r t p 2 2 8 1 2 p o r t p 3 s e t t i n g e x a m p l e 2 t h i s i s a r e g i s t e r s e t u p e x a m p l e w h e r e b o t h f l d o u t p u t a n d d i g i t w a v e f o r m o u t p u t a r e u s e d . i n t h i s c a s e , b e c a u s e t h e d i g i t d i s p l a y o u t p u t i s a u t o m a t i c a l l y g e n e r a t e d , t h e r e i s n o n e e d t o s e t t h e d i s p l a y p a t t e r n i n t h e f l d a u t o m a t i c d i s p l a y r a m . 1 1 1 1 1 1 1 1 f l d 3 2 ( s e g o u t p u t ) f l d 3 3 ( s e g o u t p u t ) f l d 3 4 ( s e g o u t p u t ) f l d 3 5 ( s e g o u t p u t ) f l d 3 6 ( s e g o u t p u t ) f l d 3 7 ( s e g o u t p u t ) f l d 3 8 ( s e g o u t p u t ) f l d 3 9 ( s e g o u t p u t ) f l d 1 6 ( s e g o u t p u t ) f l d 1 7 ( s e g o u t p u t ) f l d 1 8 ( s e g o u t p u t ) f l d 1 9 ( s e g o u t p u t ) f l d 2 0 ( s e g o u t p u t ) f l d 2 1 ( s e g o u t p u t ) f l d 2 2 ( s e g o u t p u t ) f l d 2 3 ( s e g o u t p u t ) f l d 0 ( d i g o u t p u t ) f l d 1 ( d i g o u t p u t ) f l d 2 ( d i g o u t p u t ) f l d 3 ( d i g o u t p u t ) f l d 4 ( d i g o u t p u t ) f l d 5 ( d i g o u t p u t ) f l d 6 ( d i g o u t p u t ) f l d 7 ( d i g o u t p u t ) 1 1 1 1 1 1 1 1 f l d 8 ( d i g o u t p u t ) f l d 9 ( d i g o u t p u t ) f l d 1 0 ( d i g o u t p u t ) f l d 1 1 ( d i g o u t p u t ) f l d 1 2 ( s e g o u t p u t ) f l d 1 3 ( s e g o u t p u t ) f l d 1 4 ( s e g o u t p u t ) f l d 1 5 ( s e g o u t p u t ) 1 1 1 1 0 0 0 0 f l d 2 4 ( s e g o u t p u t ) f l d 2 5 ( s e g o u t p u t ) f l d 2 6 ( s e g o u t p u t ) f l d 2 7 ( s e g o u t p u t ) f l d 2 8 ( s e g o u t p u t ) f l d 2 9 ( s e g o u t p u t ) f l d 3 0 ( s e g o u t p u t ) f l d 3 1 ( s e g o u t p u t ) p o r t p 4 1 1 1 1 0 0 0 0 f l d 4 0 ( s e g o u t p u t ) f l d 4 1 ( s e g o u t p u t ) f l d 4 2 ( s e g o u t p u t ) f l d 4 3 ( s e g o u t p u t ) f l d 4 4 ( p o r t o u t p u t ) f l d 4 5 ( p o r t o u t p u t ) f l d 4 6 ( p o r t o u t p u t ) f l d 4 7 ( p o r t o u t p u t ) p o r t p 5 0 0 0 0 0 0 0 0 f l d 4 8 ( p o r t o u t p u t ) f l d 4 9 ( p o r t o u t p u t ) f l d 5 0 ( p o r t o u t p u t ) f l d 5 1 ( p o r t o u t p u t ) f l d 5 2 ( p o r t o u t p u t ) f l d 5 3 ( p o r t o u t p u t ) f l d 5 4 ( p o r t o u t p u t ) f l d 5 5 ( p o r t o u t p u t ) p o r t p 6 d i g o u t p u t: t h i s o u t p u t i s c o n n e c t e d t o d i g i t o f t h e f l d . s e g o u t p u t: t h i s o u t p u t i s c o n n e c t e d t o s e g m e n t o f t h e f l d . p o r t o u t p u t: t h i s o u t p u t i s g e n e r a l - p u r p o s e p o r t ( u s e d b y p r o g r a m ) . t h e c o n t e n t s o f d i g i t o u t p u t s e t s w i t c h r e g i s t e r s ( 0 e f 2 1 6 , 0 e f 3 1 6 ) f l d / p o r t s w i t c h r e g i s t e r s ( 0 e f 9 1 6 t o 0 e f b 1 6 ) n u m b e r o f s e g m e n t s n u m b e r o f d i g i t s t h e c o n t e n t s o f d i g i t o u t p u t s e t s w i t c h r e g i s t e r s ( 0 e f 2 1 6 , 0 e f 3 1 6 ) f l d / p o r t s w i t c h r e g i s t e r s ( 0 e f 9 1 6 t o 0 e f b 1 6 ) d i g o u t p u t: t h i s o u t p u t i s c o n n e c t e d t o d i g i t o f t h e f l d . s e g o u t p u t: t h i s o u t p u t i s c o n n e c t e d t o s e g m e n t o f t h e f l d . p o r t o u t p u t: t h i s o u t p u t i s g e n e r a l - p u r p o s e p o r t ( u s e d b y p r o g r a m ) .
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 50 fig. 50 fld automatic display ram assignment fld automatic display ram the fld automatic display ram uses the 224 bytes of addresses 0e00 16 to 0edf 16 . for fld, the 3 modes of 16-timing ordinary mode, 16-timing gradation display mode and 32-timing mode are available depending on the number of timings and the use/not use of gradation display. the automatic display ram in each mode is as follows: (1) 16-timing?rdinary mode this mode is used when the display timing is 16 or less. the 112 bytes of addresses 0e70 16 to 0edf 16 are used as a fld display data store area. because addresses 0e00 16 to 0e6f 16 are not used as the automatic display ram, they can be the ordinary ram. (2) 16-timing?radation display mode this mode is used when the display timing is 16 or less, in which mode each segment can be set for dark or bright display. the 224 bytes of addresses 0e00 16 to 0edf 16 are used. the 112 bytes of addresses 0e70 16 to 0edf 16 are used as an fld display data store area, while the 112 bytes of addresses 0e00 16 to 0e6f 16 are used as a gradation display control data store area. (3) 32-timing mode this mode is used when the display timing is 16 or greater. this mode can be used for up to 32-timing. the 224 bytes of addresses 0e00 16 to 0edf 16 are used as an fld display data store area. the fld data pointer (address 0ef8 16 ) is a register to count dis- play timings. this pointer has a reload register. when the pointer underflow occurs, it starts counting over again after being re- loaded with the initial value in the reload register. make sure that (the timing counts 1) is set to the fld data pointer. when writing data to this address, the data is written to the fld data pointer re- load register; when reading data from this address, the value in the fld data pointer is read. 1 6 - t i m i n g o r d i n a r y m o d e 0 e d f 1 6 0 e 7 0 1 6 0 e 0 0 1 6 0 e d f 1 6 0 e 0 0 1 6 0 e d f 1 6 0 e 7 0 1 6 0 e 0 0 1 6 1 6 - t i m i n g g r a d a t i o n d i s p l a y m o d e 3 2 - t i m i n g m o d e 1 t o 3 2 t i m i n g d i s p l a y d a t a s t o r e d a r e a g r a d a t i o n d i s p l a y c o n t r o l d a t a s t o r e d a r e a 1 t o 1 6 t i m i n g d i s p l a y d a t a s t o r e d a r e a 1 t o 1 6 t i m i n g d i s p l a y d a t a s t o r e d a r e a n o t u s e d
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 51 data setup (1) 16-timing ordinary mode the area of addresses 0e70 16 to 0edf 16 are used as a fld au- tomatic display ram. when data is stored in the fld automatic display ram, the last data of fld port p6 is stored at address 0e70 16 , the last data of fld port p5 is stored at address 0e80 16 , the last data of fld port p4 is stored at address 0e90 16 , the last data of fld port p3 is stored at address 0ea0 16 , the last data of fld port p1 is stored at address 0eb0 16 , the last data of fld port p0 is stored at address 0ec0 16 , and the last data of fld port p2 is stored at address 0ed0 16 , to assign in sequence from the last data respectively. the first data of the fld port p6, p5, p4, p3, p1, p0, and p2 is stored at an address which adds the value of (the timing number 1) to the corresponding addresses 0e70 16 , 0e80 16 , 0e90 16 , 0ea0 16 , 0eb0 16 , 0ec0 16 and 0ed0 16 . set the fld data pointer reload register to the value given by (the timing number 1). fig. 51 example of using fld automatic display ram in 16-timing ordinary mode (2) 16-timing gradation display mode display data setting is performed in the same way as that of the 16-timing ordinary mode. gradation display control data is ar- ranged at an address resulting from subtracting 0070 16 from the display data store address of each timing and pin. bright display is performed by setting 0 , and dark display is performed by setting 1 . (3) 32-timing mode the area of addresses 0e00 16 to 0edf 16 is used as a fld auto- matic display ram. when data is stored in the fld automatic display ram, the last data of fld port p6 is stored at address 0e00 16 , the last data of fld port p5 is stored at address 0e20 16 , the last data of fld port p4 is stored at address 0e40 16 , the last data of fld port p3 is stored at address 0e60 16 , the last data of fld port p1 is stored at address 0e80 16 , the last data of fld port p0 is stored at address 0ea0 16 , and the last data of fld port p2 is stored at address 0ec0 16 , to assign in sequence from the last data respectively. the first data of the fld port p6, p5, p4, p3, p1, p0, and p2 is stored at an address which adds the value of (the timing number 1) to the corresponding addresses 0e00 16 , 0e20 16 , 0e40 16 , 0e60 16 , 0e80 16 , 0ea0 16 and 0ec0 16 . set the fld data pointer reload register to the value given by (the timing number 1). n u m b e r o f t i m i n g : 8 ( f l d d a t a p o i n t e r r e l o a d r e g i s t e r = 7 ) a d d r e s s 0 e 8 f 1 6 0 e 7 1 1 6 0 e 7 2 1 6 0 e 7 3 1 6 0 e 7 4 1 6 0 e 7 5 1 6 0 e 7 6 1 6 0 e 7 7 1 6 0 e 7 8 1 6 0 e 7 9 1 6 0 e 7 a 1 6 0 e 7 b 1 6 0 e 7 c 1 6 0 e 7 d 1 6 0 e 7 e 1 6 0 e 7 f 1 6 0 e 8 0 1 6 0 e 8 1 1 6 0 e 8 2 1 6 0 e 8 3 1 6 0 e 8 4 1 6 0 e 8 5 1 6 0 e 8 6 1 6 0 e 8 7 1 6 0 e 8 8 1 6 0 e 8 9 1 6 0 e 8 a 1 6 0 e 8 b 1 6 0 e 8 c 1 6 0 e 8 d 1 6 0 e 8 e 1 6 0 e 9 0 1 6 0 e 9 1 1 6 0 e 9 2 1 6 0 e 9 3 1 6 0 e 9 4 1 6 0 e 9 5 1 6 0 e 9 6 1 6 0 e 9 7 1 6 0 e 9 8 1 6 0 e 9 9 1 6 0 e 9 a 1 6 0 e 9 b 1 6 0 e 9 c 1 6 0 e 9 d 1 6 0 e 9 e 1 6 0 e 9 f 1 6 0 e a 1 1 6 0 e a 2 1 6 0 e a 3 1 6 0 e a 4 1 6 0 e a 5 1 6 0 e a 6 1 6 0 e a 7 1 6 0 e a 8 1 6 0 e a 9 1 6 0 e a a 1 6 0 e a b 1 6 0 e a c 1 6 0 e a d 1 6 0 e a e 1 6 0 e a f 1 6 0 e a 0 1 6 0 e 7 0 1 6 t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 6 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 6 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 5 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 5 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 4 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 4 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 3 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 3 ) 76543210 b i t a d d r e s s 0 e b 1 1 6 0 e b 2 1 6 0 e b 3 1 6 0 e b 4 1 6 0 e b 5 1 6 0 e b 6 1 6 0 e b 7 1 6 0 e b 8 1 6 0 e b 9 1 6 0 e b a 1 6 0 e b b 1 6 0 e b c 1 6 0 e b d 1 6 0 e b e 1 6 0 e b f 1 6 0 e b 0 1 6 t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 1 ) f l d p 1 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 1 ) 7 6 5 4 3 2 1 0 b i t 0 e c 1 1 6 0 e c 2 1 6 0 e c 3 1 6 0 e c 4 1 6 0 e c 5 1 6 0 e c 6 1 6 0 e c 7 1 6 0 e c 8 1 6 0 e c 9 1 6 0 e c a 1 6 0 e c b 1 6 0 e c c 1 6 0 e c d 1 6 0 e c e 1 6 0 e c f 1 6 0 e c 0 1 6 0 e d 1 1 6 0 e d 2 1 6 0 e d 3 1 6 0 e d 4 1 6 0 e d 5 1 6 0 e d 6 1 6 0 e d 7 1 6 0 e d 8 1 6 0 e d 9 1 6 0 e d a 1 6 0 e d b 1 6 0 e d c 1 6 0 e d d 1 6 0 e d e 1 6 0 e d f 1 6 0 e d 0 1 6 t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 0 ) f l d p 0 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 0 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 2 ) f l d p 2 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 2 ) f l d p 3 d a t a a r e a f l d p 4 d a t a a r e a f l d p 6 d a t a a r e a f l d p 5 d a t a a r e a
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 52 fig. 52 example of using fld automatic display ram in 16-timing gradation display mode n u m b e r o f t i m i n g : 1 5 ( f l d d a t a p o i n t e r r e l o a d r e g i s t e r = 1 4 ) a d d r e s s 0 e 8 f 1 6 0 e 7 1 1 6 0 e 7 2 1 6 0 e 7 3 1 6 0 e 7 4 1 6 0 e 7 5 1 6 0 e 7 6 1 6 0 e 7 7 1 6 0 e 7 8 1 6 0 e 7 9 1 6 0 e 7 a 1 6 0 e 7 b 1 6 0 e 7 c 1 6 0 e 7 d 1 6 0 e 7 e 1 6 0 e 7 f 1 6 0 e 8 0 1 6 0 e 8 1 1 6 0 e 8 2 1 6 0 e 8 3 1 6 0 e 8 4 1 6 0 e 8 5 1 6 0 e 8 6 1 6 0 e 8 7 1 6 0 e 8 8 1 6 0 e 8 9 1 6 0 e 8 a 1 6 0 e 8 b 1 6 0 e 8 c 1 6 0 e 8 d 1 6 0 e 8 e 1 6 0 e 9 0 1 6 0 e 9 1 1 6 0 e 9 2 1 6 0 e 9 3 1 6 0 e 9 4 1 6 0 e 9 5 1 6 0 e 9 6 1 6 0 e 9 7 1 6 0 e 9 8 1 6 0 e 9 9 1 6 0 e 9 a 1 6 0 e 9 b 1 6 0 e 9 c 1 6 0 e 9 d 1 6 0 e 9 e 1 6 0 e 9 f 1 6 0 e a 1 1 6 0 e a 2 1 6 0 e a 3 1 6 0 e a 4 1 6 0 e a 5 1 6 0 e a 6 1 6 0 e a 7 1 6 0 e a 8 1 6 0 e a 9 1 6 0 e a a 1 6 0 e a b 1 6 0 e a c 1 6 0 e a d 1 6 0 e a e 1 6 0 e a f 1 6 0 e a 0 1 6 0 e b 1 1 6 0 e b 2 1 6 0 e b 3 1 6 0 e b 4 1 6 0 e b 5 1 6 0 e b 6 1 6 0 e b 7 1 6 0 e b 8 1 6 0 e b 9 1 6 0 e b a 1 6 0 e b b 1 6 0 e b c 1 6 0 e b d 1 6 0 e b e 1 6 0 e b f 1 6 0 e b 0 1 6 0 e 7 0 1 6 t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 6 ) 76543210 b i t t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 5 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 4 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 3 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 1 ) f l d p 6 d a t a a r e a f l d p 5 d a t a a r e a f l d p 4 d a t a a r e a f l d p 3 d a t a a r e a f l d p 1 d a t a a r e a 0 e c 1 1 6 0 e c 2 1 6 0 e c 3 1 6 0 e c 4 1 6 0 e c 5 1 6 0 e c 6 1 6 0 e c 7 1 6 0 e c 8 1 6 0 e c 9 1 6 0 e c a 1 6 0 e c b 1 6 0 e c c 1 6 0 e c d 1 6 0 e c e 1 6 0 e c f 1 6 0 e c 0 1 6 t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 0 ) f l d p 0 d a t a a r e a 0 e d 1 1 6 0 e d 2 1 6 0 e d 3 1 6 0 e d 4 1 6 0 e d 5 1 6 0 e d 6 1 6 0 e d 7 1 6 0 e d 8 1 6 0 e d 9 1 6 0 e d a 1 6 0 e d b 1 6 0 e d c 1 6 0 e d d 1 6 0 e d e 1 6 0 e d f 1 6 0 e d 0 1 6 t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 2 ) f l d p 2 d a t a a r e a a d d r e s s 0 e 1 f 1 6 0 e 0 1 1 6 0 e 0 2 1 6 0 e 0 3 1 6 0 e 0 4 1 6 0 e 0 5 1 6 0 e 0 6 1 6 0 e 0 7 1 6 0 e 0 8 1 6 0 e 0 9 1 6 0 e 0 a 1 6 0 e 0 b 1 6 0 e 0 c 1 6 0 e 0 d 1 6 0 e 0 e 1 6 0 e 0 f 1 6 0 e 1 0 1 6 0 e 1 1 1 6 0 e 1 2 1 6 0 e 1 3 1 6 0 e 1 4 1 6 0 e 1 5 1 6 0 e 1 6 1 6 0 e 1 7 1 6 0 e 1 8 1 6 0 e 1 9 1 6 0 e 1 a 1 6 0 e 1 b 1 6 0 e 1 c 1 6 0 e 1 d 1 6 0 e 1 e 1 6 0 e 2 0 1 6 0 e 2 1 1 6 0 e 2 2 1 6 0 e 2 3 1 6 0 e 2 4 1 6 0 e 2 5 1 6 0 e 2 6 1 6 0 e 2 7 1 6 0 e 2 8 1 6 0 e 2 9 1 6 0 e 2 a 1 6 0 e 2 b 1 6 0 e 2 c 1 6 0 e 2 d 1 6 0 e 2 e 1 6 0 e 2 f 1 6 0 e 3 1 1 6 0 e 3 2 1 6 0 e 3 3 1 6 0 e 3 4 1 6 0 e 3 5 1 6 0 e 3 6 1 6 0 e 3 7 1 6 0 e 3 8 1 6 0 e 3 9 1 6 0 e 3 a 1 6 0 e 3 b 1 6 0 e 3 c 1 6 0 e 3 d 1 6 0 e 3 e 1 6 0 e 3 f 1 6 0 e 3 0 1 6 0 e 4 1 1 6 0 e 4 2 1 6 0 e 4 3 1 6 0 e 4 4 1 6 0 e 4 5 1 6 0 e 4 6 1 6 0 e 4 7 1 6 0 e 4 8 1 6 0 e 4 9 1 6 0 e 4 a 1 6 0 e 4 b 1 6 0 e 4 c 1 6 0 e 4 d 1 6 0 e 4 e 1 6 0 e 4 f 1 6 0 e 4 0 1 6 0 e 0 0 1 6 t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 6 ) 76 5 43 2 1 0 b i t t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 5 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 4 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 3 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 1 ) f l d p 6 g r a d a t i o n d i s p l a y d a t a a r e a f l d p 5 g r a d a t i o n d i s p l a y d a t a a r e a f l d p 4 g r a d a t i o n d i s p l a y d a t a a r e a f l d p 3 g r a d a t i o n d i s p l a y d a t a a r e a f l d p 1 g r a d a t i o n d i s p l a y d a t a a r e a 0 e 5 1 1 6 0 e 5 2 1 6 0 e 5 3 1 6 0 e 5 4 1 6 0 e 5 5 1 6 0 e 5 6 1 6 0 e 5 7 1 6 0 e 5 8 1 6 0 e 5 9 1 6 0 e 5 a 1 6 0 e 5 b 1 6 0 e 5 c 1 6 0 e 5 d 1 6 0 e 5 e 1 6 0 e 5 f 1 6 0 e 5 0 1 6 t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 0 ) f l d p 0 g r a d a t i o n d i s p l a y d a t a a r e a 0 e 6 1 1 6 0 e 6 2 1 6 0 e 6 3 1 6 0 e 6 4 1 6 0 e 6 5 1 6 0 e 6 6 1 6 0 e 6 7 1 6 0 e 6 8 1 6 0 e 6 9 1 6 0 e 6 a 1 6 0 e 6 b 1 6 0 e 6 c 1 6 0 e 6 d 1 6 0 e 6 e 1 6 0 e 6 f 1 6 0 e 6 0 1 6 t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 2 ) f l d p 2 g r a d a t i o n d i s p l a y d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 6 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 5 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 4 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 3 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 1 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 0 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 2 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 6 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 5 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 4 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 3 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 1 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 0 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 2 )
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 53 0 e 8 f 1 6 0 e 7 1 1 6 0 e 7 2 1 6 0 e 7 3 1 6 0 e 7 4 1 6 0 e 7 5 1 6 0 e 7 6 1 6 0 e 7 7 1 6 0 e 7 8 1 6 0 e 7 9 1 6 0 e 7 a 1 6 0 e 7 b 1 6 0 e 7 c 1 6 0 e 7 d 1 6 0 e 7 e 1 6 0 e 7 f 1 6 0 e 8 0 1 6 0 e 8 1 1 6 0 e 8 2 1 6 0 e 8 3 1 6 0 e 8 4 1 6 0 e 8 5 1 6 0 e 8 6 1 6 0 e 8 7 1 6 0 e 8 8 1 6 0 e 8 9 1 6 0 e 8 a 1 6 0 e 8 b 1 6 0 e 8 c 1 6 0 e 8 d 1 6 0 e 8 e 1 6 0 e 9 0 1 6 0 e 9 1 1 6 0 e 9 2 1 6 0 e 9 3 1 6 0 e 9 4 1 6 0 e 9 5 1 6 0 e 9 6 1 6 0 e 9 7 1 6 0 e 9 8 1 6 0 e 9 9 1 6 0 e 9 a 1 6 0 e 9 b 1 6 0 e 9 c 1 6 0 e 9 d 1 6 0 e 9 e 1 6 0 e 9 f 1 6 0 e a 1 1 6 0 e a 2 1 6 0 e a 3 1 6 0 e a 4 1 6 0 e a 5 1 6 0 e a 6 1 6 0 e a 7 1 6 0 e a 8 1 6 0 e a 9 1 6 0 e a a 1 6 0 e a b 1 6 0 e a c 1 6 0 e a d 1 6 0 e a e 1 6 0 e a f 1 6 0 e a 0 1 6 0 e b 1 1 6 0 e b 2 1 6 0 e b 3 1 6 0 e b 4 1 6 0 e b 5 1 6 0 e b 6 1 6 0 e b 7 1 6 0 e b 8 1 6 0 e b 9 1 6 0 e b a 1 6 0 e b b 1 6 0 e b c 1 6 0 e b d 1 6 0 e b e 1 6 0 e b f 1 6 0 e b 0 1 6 0 e 7 0 1 6 76543210 0 e c 1 1 6 0 e c 2 1 6 0 e c 3 1 6 0 e c 4 1 6 0 e c 5 1 6 0 e c 6 1 6 0 e c 7 1 6 0 e c 8 1 6 0 e c 9 1 6 0 e c a 1 6 0 e c b 1 6 0 e c c 1 6 0 e c d 1 6 0 e c e 1 6 0 e c f 1 6 0 e c 0 1 6 0 e d 1 1 6 0 e d 2 1 6 0 e d 3 1 6 0 e d 4 1 6 0 e d 5 1 6 0 e d 6 1 6 0 e d 7 1 6 0 e d 8 1 6 0 e d 9 1 6 0 e d a 1 6 0 e d b 1 6 0 e d c 1 6 0 e d d 1 6 0 e d e 1 6 0 e d f 1 6 0 e d 0 1 6 0 e 1 f 1 6 0 e 0 1 1 6 0 e 0 2 1 6 0 e 0 3 1 6 0 e 0 4 1 6 0 e 0 5 1 6 0 e 0 6 1 6 0 e 0 7 1 6 0 e 0 8 1 6 0 e 0 9 1 6 0 e 0 a 1 6 0 e 0 b 1 6 0 e 0 c 1 6 0 e 0 d 1 6 0 e 0 e 1 6 0 e 0 f 1 6 0 e 1 0 1 6 0 e 1 1 1 6 0 e 1 2 1 6 0 e 1 3 1 6 0 e 1 4 1 6 0 e 1 5 1 6 0 e 1 6 1 6 0 e 1 7 1 6 0 e 1 8 1 6 0 e 1 9 1 6 0 e 1 a 1 6 0 e 1 b 1 6 0 e 1 c 1 6 0 e 1 d 1 6 0 e 1 e 1 6 0 e 2 0 1 6 0 e 2 1 1 6 0 e 2 2 1 6 0 e 2 3 1 6 0 e 2 4 1 6 0 e 2 5 1 6 0 e 2 6 1 6 0 e 2 7 1 6 0 e 2 8 1 6 0 e 2 9 1 6 0 e 2 a 1 6 0 e 2 b 1 6 0 e 2 c 1 6 0 e 2 d 1 6 0 e 2 e 1 6 0 e 2 f 1 6 0 e 3 1 1 6 0 e 3 2 1 6 0 e 3 3 1 6 0 e 3 4 1 6 0 e 3 5 1 6 0 e 3 6 1 6 0 e 3 7 1 6 0 e 3 8 1 6 0 e 3 9 1 6 0 e 3 a 1 6 0 e 3 b 1 6 0 e 3 c 1 6 0 e 3 d 1 6 0 e 3 e 1 6 0 e 3 f 1 6 0 e 3 0 1 6 0 e 4 1 1 6 0 e 4 2 1 6 0 e 4 3 1 6 0 e 4 4 1 6 0 e 4 5 1 6 0 e 4 6 1 6 0 e 4 7 1 6 0 e 4 8 1 6 0 e 4 9 1 6 0 e 4 a 1 6 0 e 4 b 1 6 0 e 4 c 1 6 0 e 4 d 1 6 0 e 4 e 1 6 0 e 4 f 1 6 0 e 4 0 1 6 0 e 0 0 1 6 76543 2 1 0 0 e 5 1 1 6 0 e 5 2 1 6 0 e 5 3 1 6 0 e 5 4 1 6 0 e 5 5 1 6 0 e 5 6 1 6 0 e 5 7 1 6 0 e 5 8 1 6 0 e 5 9 1 6 0 e 5 a 1 6 0 e 5 b 1 6 0 e 5 c 1 6 0 e 5 d 1 6 0 e 5 e 1 6 0 e 5 f 1 6 0 e 5 0 1 6 0 e 6 1 1 6 0 e 6 2 1 6 0 e 6 3 1 6 0 e 6 4 1 6 0 e 6 5 1 6 0 e 6 6 1 6 0 e 6 7 1 6 0 e 6 8 1 6 0 e 6 9 1 6 0 e 6 a 1 6 0 e 6 b 1 6 0 e 6 c 1 6 0 e 6 d 1 6 0 e 6 e 1 6 0 e 6 f 1 6 0 e 6 0 1 6 n u m b e r o f t i m i n g : 2 0 ( f l d d a t a p o i n t e r r e l o a d r e g i s t e r = 1 9 ) a d d r e s s b i t f l d p 1 d a t a a r e a t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 0 ) f l d p 0 d a t a a r e a t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 2 ) f l d p 2 d a t a a r e a t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 6 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 5 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 4 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 3 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 1 ) f l d p 6 d a t a a r e a f l d p 5 d a t a a r e a f l d p 4 d a t a a r e a f l d p 3 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 1 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 0 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 2 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 6 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 5 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 4 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 3 ) a d d r e s s b i t fig. 53 example of using fld automatic display ram in 32-timing mode
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 54 timing setting each timing is set by the fldc mode register, tdisp time set reg- ister, toff1 time set register, and toff2 time set register. (1) tdisp time setting the tdisp time means the length of display timing. in non-grada- tion display mode, it consists of the fld display output term and the toff1 time. in gradation display mode, it consists of the display output term and the toff1 time plus a low signal output term for dark display. set the tdisp time by the tdisp counter count source selection bit of the fldc mode register and the tdisp time set register. supposing that the value of the tdisp time set register is n, the tdisp time is represented as tdisp = (n+1) ? t (t: count source). when the tdisp counter count source selection bit of the fldc mode register is ? and the value of the tdisp time set reg- ister is 200 (c8 16 ), the tdisp time is: tdisp = (200 + 1) ? 4.0 s (at x in = 4 mhz) = 804 s. when reading the tdisp time set register, the counting value is read out. (2) toff1 time setting the toff1 time means a non-output (low signal output) time to pre- vent blurring of fld and for dimmer display. use the toff1 time set register to set this toff1 time. make sure the value set to toff1 is smaller than tdisp and toff2. supposing that the value of the toff1 time set register is n1, the toff1 time is represented as toff1 = n1 ? t. when the tdisp counter count source selection bit of the fldc mode register is ? and the value of the toff1 time set reg- ister is 30 (1e 16 ), toff1 = 30 ? 4.0 s (at x in = 4 mhz) = 120 s. be sure to set the value of 03 16 or more to the toff1 time set reg- ister (address 0ef6 16 ). (3) toff2 time setting the toff2 time is time for dark display. for bright display, the fld display output remains effective until the counter that is counting tdisp underflows. for dark display, however, ? (or ?ff? signal is output when the counter that is counting toff2 underflows. this toff2 time setting is valid only for fld ports which are in the gra- dation display mode and whose gradation display control ram value is ??. set the toff2 time by the toff2 time set register. make sure the value set to toff2 is smaller than tdisp but larger than toff1. sup- posing that the value of the toff2 time set register is n2, the toff2 time is represented as toff2 = n2 ? t. when the tdisp counter count source selection bit of the fldc mode register is ??and the value of the toff2 time set register is 180 (b4 16 ), toff2 = 180 ? 4.0 s (at x in = 4 mhz) = 720 s. when bit 7 of the fld output control register (address 0efc 16 ) is set to ?? be sure to set the value of 03 16 or more to the toff2 time set register (address 0ef7 16 ). fig. 54 fld and digit output timing toff1 t d i s p t o f f 1 t o f f 2 tdis p gradation display mode is not selected (address 0ef4 16 bit 5 = ?) gradation display mode is selected and set for bright display (address 0ef4 16 bit 5 = ? and the corresponding gradation dis p la y control data = 0 ) l o w o u t p u t t e r m f o r b l u r r i n g p r e v e n t i o n d i s p l a y o u t p u t t e r m d i s p l a y o u t p u t t e r m low output term for blurring prevention gradation display mode is selected and set for dark display (address 0ef4 16 bit 5 = ? and the corresponding gradation display control data = 1? l o w o u t p u t t e r m f o r d a r k d i s p l a y
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 55 fig. 55 timing using digit interrupt fld automatic display start automatic display starts by setting both the automatic display con- trol bit (bit 0 of address 0ef4 16 ) and the display start bit (bit 1 of address 0ef4 16 ) to 1 . the ram contents at a location apart from the start address of the automatic display ram for each port by (fld data pointer (address 0ef8 16 ) 1) are output to each port. the fld data pointer (address 0ef8 16 ) counts down in the tdisp interval. when the count results in ff 16 , the pointer is reloaded and starts counting over again. before setting the display start bit (bit 1 of address 0ef4 16 ) to 1 , be sure to set the fld/port switch registers, digit output set switch registers, fldc mode register, tdisp time set register, toff1 time set register, toff2 time set regis- ter, and fld data pointer. during fld automatic display, the display start bit always keeps 1 , and fld automatic display can be interrupted by writing 0 to this bit. key-scan and interrupt either the fld digit interrupt or fld blanking interrupt can be se- lected using the tscan control bits (bits 2, 3 of address 0ef4 16 ). the fld digit interrupt is generated when the toff1 time in each timing expires (at rising edge of digit output). key scanning that makes use of fld digits can be achieved using each fld digit in- terrupt. to use fld digit interrupts for key scanning, follow the procedure described below: (1) read the port value each time the interrupt occurs. (2) the key is fixed on the last digit interrupt. the output digit positions can be determined by reading the fld data pointer (address 0ef8 16 ). f l d d i g i t o u t p u t t d i s p t n t n - 1t n - 2t 4t 3t 2t 1 t n t n - 1t n - 2 t 4 t o f f 1 f l d d i g i t i n t e r r u p t g e n e r a t e d a t t h e r i s i n g e d g e o f d i g i t ( e a c h t i m i n g ) r e p e a t c y c l e
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 56 fig. 56 timing using fld blanking interrupt the fld blanking interrupt is generated when the fld data pointer (address 0ef8 16 ) reaches ff 16 . the fld automatic dis- play output is turned off for a duration of 1 ? tdisp, 2 ? tdisp, or 3 ? tdisp depending on post-interrupt settings. during this time, key scanning that makes use of fld segments can be achieved. when the key scanning is performed with the segment during key-scan blanking time tscan, follow the procedure described below: (1) write 0 to the automatic display control bit (bit 0 of address 0ef4 16 ). (2) set the port corresponding to the segment for key scanning to the output port. (3) perform key scanning. (4) write 1 to the automatic display control bit. when performing a key-scan according to the above steps 1 to 4, take the following points into consideration. 1. do not set the display start bit (bit 1 of address 0ef4 16 ) to 0 . 2. do not set 1 in the ports corresponding to digits. t d i s p t s c a n t nt n - 1 t n - 2 t 4 t 3 t 2 t 1 t nt n - 1t n - 2 s e g m e n t s e t t i n g b y s o f t w a r e f l d b l a n k i n g i n t e r r u p t g e n e r a t e d a t t h e f a l l i n g o f e d g e o f t h e l a s t t i m i n g f l d d i g i t o u t p u t r e p e a t c y c l e
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 57 p6 4 to p6 7 expansion function ports p6 4 to p6 7 are cmos output structure. fld digit outputs can be increased as many as 16 lines by connecting a decoder converting 4-bit to 16-bit data to these ports. p6 4 to p6 7 have the function to allow for connection to a decoder converting 4-bit to 16-bit data. (1) p6 4 to p6 7 toff invalid function this function disables the toff1 time and toff2 time and outputs display data for the duration of tdisp. (see figure 57.) this can be achieved by setting the p6 4 to p6 7 toff invalid bit (bit 2 of address 0efc 16 ) to 1 . (2) dimmer signal output function this function allows a dimmer signal creation signal to be output from dim out (p7 3 ). the dimmer function can be achieved by con- trolling the decoder with this signal. (see figure 57.) this function can be set by setting p7 3 dimmer output control bit (bit 4 of ad- dress 0efc 16 ) to 1 . unlike the toff section generating/nothing function, this function disables all display data. fig. 57 p6 4 to p6 7 fld output pulses (3) p6 4 to p6 7 fld output reverse function p6 4 to p6 7 have the function to reverse the polarity of the fld out- put. this function is useful in adjusting the polarity when using an externally installed driver. the output polarity can be reversed by setting the p6 4 to p6 7 out- put reverse bit of the fld output control register (bit 0 of address 0efc 16 ) to 1 . in the case of gradation display mode and dark display, p6 4 to p6 7 toff invalid function is disabled. t d i s p t o f f 2 t o f f 1 f o r d i m m e r s i g n a l d i m o u t ( p 7 3 ) f l d o u t p u t g r a d a t i o n d i s p l a y m o d e i s n o t s e l e c t e d g r a d a t i o n d i s p l a y m o d e i s s e l e c t e d a n d s e t f o r b r i g h t d i s p l a y ( g r a d a t i o n d i s p l a y c o n t r o l d a t a = 0 ) g r a d a t i o n d i s p l a y m o d e i s s e l e c t e d a n d s e t f o r d a r k d i s p l a y ( g r a d a t i o n d i s p l a y c o n t r o l d a t a = 1 ) g r a d a t i o n d i s p l a y m o d e i s s e l e c t e d a n d t o f f 2 s e t / r e s e t s w i t c h b i t i s 1 ( g r a d a t i o n d i s p l a y c o n t r o l d a t a = 1 ) o u t p u t s e l e c t i n g p 6 4 t o p 6 7 t o f f i n v a l i d
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 58 toff2 set/reset switch function in gradation display mode, the values set by the toff2 time set reg- ister (toff2) are effective. when the toff2 set/reset switch bit of fld output control register (bit 7 of address 0efc 16 ) is 0 , ram data is output to the fld output ports (set) at the time that is set by toff1 and it is turned to 0 (reset) at the time that is set by toff2. when toff2 set/reset switch bit is 1 , ram data is output (set) at the time that is set by toff2 and it is turned to 0 (re- set) when the tdisp time expires. in the case of gradation display mode and dark display, the toff section generate/nothing function is disabled. toff section generate/nothing function the function is for reduction of useless noises which generated as every switching of ports, because of the combined capacity of among fld ports. when the continuous data is output to each fld port, the toff1 section of the continuous parts is not gener- ated. (see figure 58) fig. 58 toff section generating/nothing function if it needs toff1 section on fld pulses, set the generating /not of cmos port toff section selection bit (bit 5 of address 0efc 16 ) to 1 and set the generating /not of high-breakdown-voltage port toff section selection bit to 1 . high-breakdown-voltage ports (p2, p0, p1, p3, p4, p5, p6 3 to p6 0 , total 52 pins) generate toff1 section by setting the generating /not of high-breakdown-voltage port toff section selection bit to 1 . the cmos ports (p6 4 to p6 7 , total 4 pins ) generate toff1 section by setting the generating /not of cmos port toff section selection bit to 1 . p 1 x p 2 x p 1 x p 2 x h o u t p u t t d i s p t o f f 1 s e c t i o n o f t o f f 1 i s n o t g e n e r a t e d b e c a u s e o f o u t p u t i s t h e s a m e . o u t p u t w a v e f o r m w h e n g e n e r a t i n g / n o t o f h i g h - b r e a k d o w n v o l t a g e p o r t t o f f s e c t i o n s e l e c t i o n b i t ( b i t 6 o f a d d r e s s 0 e f c 1 6 ) i s 1 . h o u t p u t h o u t p u t h o u t p u t h o u t p u t h o u t p u t h o u t p u t h o u t p u t h o u t p u t h o u t p u t h o u t p u t h o u t p u t l o u t p u t l o u t p u t l o u t p u t l o u t p u t s e c t i o n o f t o f f 1 i s n o t g e n e r a t e d b e c a u s e o f o u t p u t i s t h e s a m e . o u t p u t w a v e f o r m w h e n g e n e r a t i n g / n o t o f h i g h - b r e a k d o w n v o l t a g e p o r t t o f f s e c t i o n s e l e c t i o n b i t ( b i t 6 o f a d d r e s s 0 e f c 1 6 ) i s 0 .
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 59 fig. 59 digit pulses output function digit pulses output function p0 0 to p0 7 and p2 0 to p2 7 can output digit pulses by using the digit output set switch registers. set the digit output set switch reg- isters by setting as many consecutive 1s as the timing count from p2 0 . the contents of fld automatic display ram for the ports that have been selected for digit output are disabled, and the pulse shown in figure 59 is output automatically. the output timing consists of tdisp time and toff1 time, and toff2 time does not exist. because the contents of fld automatic display ram are dis- abled, the segment data can be changed easily even when segment data and digit data coexist at the same address in the fld automatic display ram. this function is effective in 16-timing ordinary mode and 16-timing gradation display mode. if a value is set exceeding the timing count (fld data pointer reload register s set value + 1) for any port, the output of such port is l . l o w - o r d e r 4 b i t s o f t h e d a t a p o i n t e r fedc b a 0 1 2 3 4 5 6 7 8 9 p 0 7 p 0 6 p 0 5 p 0 4 p 0 3 p 0 2 p 0 1 p 0 0 p 2 7 p 2 6 p 2 5 p 2 4 p 2 3 p 2 2 p 2 1 p 2 0 t d i s p t o f f 1
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 60 b 7 b 6b 5b 4b 3b 2b 1b 0 a d / d a c o n t r o l r e g i s t e r ( a d c o n : a d d r e s s 0 0 3 2 1 6 ) a n a l o g i n p u t p i n s e l e c t i o n b i t s b 3 b 2 b 1 b 0 0 0 0 0 : p a 0 / a n 0 0 0 0 1 : p a 1 / a n 1 0 0 1 0 : p a 2 / a n 2 0 0 1 1 : p a 3 / a n 3 0 1 0 0 : p a 4 / a n 4 0 1 0 1 : p a 5 / a n 5 0 1 1 0 : p a 6 / a n 6 0 1 1 1 : p a 7 / a n 7 1 0 0 0 : p 9 0 / s i n 3 / a n 8 1 0 0 1 : p 9 1 / s o u t 3 / a n 9 1 0 1 0 : p 9 2 / s c l k 3 / a n 1 0 1 0 1 1 : p 9 3 / s r d y 3 / a n 1 1 1 1 0 0 : p 9 4 / r t p 1 / a n 1 2 1 1 0 1 : p 9 5 / r t p 0 / a n 1 3 1 1 1 0 : p 9 6 / p w m 0 / a n 1 4 1 1 1 1 : p 9 7 / b u z 0 2 / a n 1 5 a d c o n v e r s i o n c o m p l e t i o n b i t 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r s i o n c o m p l e t e d n o t u s e d ( r e t u r n s 0 w h e n r e a d ) d a o u t p u t e n a b l e b i t 0 : d a o u t p u t d i s a b l e d 1 : d a o u t p u t e n a b l e d n o t u s e d ( r e t u r n s 0 w h e n r e a d ) a d c o n v e r s i o n r e g i s t e r ( h i g h - o r d e r ) ( a d h : a d d r e s s 0 0 3 4 1 6 ) b 7 b 0 b 7 b 6b 5b 4b 3 b 2 a d c o n v e r s i o n r e g i s t e r ( l o w - o r d e r ) ( a d l : a d d r e s s 0 0 3 3 1 6 ) b 7 b 0 b 1b 0 b 9b 8 n o t e : w h e n r e a d i n g t h e l o w - o r d e r 6 b i t s a t a d d r e s s 0 0 3 3 1 6 , 0 i s r e a d o u t . d a t a b u s av ss v ref a - d i n t e r r u p t r e q u e s t b 7b0 4 a d / d a c o n t r o l r e g i s t e r c h a n n e l s e l e c t o r c o m p a r a t o r a-d control circuit a - d c o n v e r s i o n r e g i s t e r ( h ) (address 0034 16 ) ( a d d r e s s 0 0 3 3 1 6 ) r e s i s t o r l a d d e r p a 0 / a n 0 p a 1 / a n 1 p a 2 / a n 2 p a 3 / a n 3 p a 4 / a n 4 p a 5 / a n 5 p a 6 / a n 6 p a 7 / a n 7 p 9 0 / s i n 3 / a n 8 p 9 1 / s o u t 3 / a n 9 p 9 2 / s c l k 3 / a n 1 0 p 9 3 / s r d y 3 / a n 1 1 p 9 4 / r t p 1 / a n 1 2 p 9 5 / r t p 0 / a n 1 3 p 9 6 / p w m 0 / a n 1 4 p 9 7 / b u z 0 2 / a n 1 5 a-d conversion register (l) a-d converter the 38b7 group has a 10-bit a-d converter. the a-d converter performs successive approximation conversion. [a-d conversion register] adh, adl one of these registers is a high-order register, and the other is a low-order register. the high-order 8 bits of a conversion result is stored in the a-d conversion register (high-order) (address 0034 16 ), and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the a-d conversion register (low-order) (address 0033 16 ). during a-d conversion, do not read these registers. [ad/da control register] adcon this register controls a-d converter. bits 3 to 0 are analog input pin selection bits. bit 4 is an ad conversion completion bit and 0 during a-d conversion. this bit is set to 1 upon completion of a- d conversion. a-d conversion is started by writing 0 in this bit. [comparison voltage generator] the comparison voltage generator divides the voltage between avss and v ref by 1024, and outputs the divided voltages. [channel selector] the channel selector selects one of the input ports pa 7 /an 7 pa 0 / an 0 , and p9 7 /b uz02 /an 15 to p9 0 /s in3 /an 8 and inputs it to the comparator. [comparator and control circuit] the comparator and control circuit compares an analog inputvoltage with the comparison voltage and stores the result in the a-d conversion register. when an a-d conversion is com- pleted, the control circuit sets the ad conversion completion bit and the ad conversion interrupt request bit to 1 . note that the comparator is constructed linked to a capacitor, so that set f(x in ) to at least 250 khz during a-d conversion. addition- ally, bit 7 of the cpu mode register (address 003b 16 ) must be set to 0 . fig. 61 block diagram of a-d converter fig. 60 structure of ad/da control register
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 61 d-a converter the 38b7 group has one internal d-a converter with 8-bit resolu- tion. the d-a conversion is performed by setting the value in the d-a conversion register. the result of d-a conversion is output from the da pin by setting the da output enable bit to 1 . when using the d-a converter, the pb 0 /da port direction register bit must be set to 0 (input status). the output analog voltage v is determined by the value n (deci- mal notation) in the d-a conversion register as follows: v = v ref ? n/256 (n = 0 to 255) where v ref is the reference voltage. at reset, the d-a conversion register is cleared to 00 16 , and the da output enable bit is cleared to 0 , and pb 0 /da pin becomes high impedance. the da output does not have buffers. accordingly, connect an ex- ternal buffer when driving a low-impedance load. set v cc to 3.0 v or more when using the d-a converter. fig. 62 block diagram of d-a converter fig. 63 equivalent connection circuit of d-a converter p b 0 / d a d - a c o n v e r s i o n r e g i s t e r ( 8 ) r - 2 r r e s i s t o r l a d d e r d a o u t p u t e n a b l e b i t d a t a b u s a v s s v r e f 0 1 m s b 0 1 r 2 r r 2 r r 2 r r 2 r r 2 r r 2 r r 2 r2 r l s b 2 r p b 0 / d a d - a c o n v e r s i o n r e g i s t e r d a o u t p u t e n a b l e b i t
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 62 1 4 1 / 2 x i n ( 4 m h z ) p 9 6 / p w m 0 b i t 7 b i t 0 b i t 5 m s b l s b p w m b i t 7 b i t 0 d a t a b u s x c i n 1 0 p w m r e g i s t e r ( h i g h - o r d e r ) ( a d d r e s s 0 0 3 5 1 6 ) p w m r e g i s t e r ( l o w - o r d e r ) ( a d d r e s s 0 0 3 6 1 6 ) i t i s s e t t o 1 w h e n w r i t e . p w m l a t c h ( 1 4 - b i t ) 1 4 - b i t p w m c i r c u i t w h e n t h e i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t i s s e t t o 0 t i m i n g g e n e r a t i n g u n i t f o r p w m ( 6 4 s c y c l e ) ( 4 0 9 6 s c y c l e ) p 9 6 / p w m o u t p u t s e l e c t i o n b i t p 9 6 d i r e c t i o n r e g i s t e r p 9 6 / p w m o u t p u t s e l e c t i o n b i t p 9 6 l a t c h pwm (pulse width modulation) the 38b7 group has a pwm function with a 14-bit resolution. when the oscillation frequency x in is 4 mhz, the minimum resolution bit width is 250 ns and the cycle period is 4096 s. the pwm timing generator supplies a pwm control signal based on a signal that is the frequency of the x in clock. the explanation in the rest assumes x in = 4 mhz. fig. 64 pwm block diagram
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 63 1 5 . 7 5 s 6 4 s 6 4 s6 4 s6 4 s 6 4 s m = 0 m = 7 m = 8 m = 9m = 6 3 1 6 . 0 s 1 5 . 7 5 s1 5 . 7 5 s 1 5 . 7 5 s1 5 . 7 5 s1 5 . 7 5 s p u l s e w i d t h m o d u l a t i o n r e g i s t e r h : 0 0 1 1 1 1 1 1 p u l s e w i d t h m o d u l a t i o n r e g i s t e r l : 0 0 0 1 0 1 s u b - p e r i o d s w h e r e h p u l s e w i d t h i s 1 6 . 0 s : m = 8 , 2 4 , 3 2 , 4 0 , 5 6 s u b - p e r i o d s w h e r e h p u l s e w i d t h i s 1 5 . 7 5 s : m = a l l o t h e r v a l u e s 4 0 9 6 s data setup the pwm output pin also function as port p9 6 . set port p9 6 to be the pwm output pin by setting bit 0 of the pwm control register (address 0026 16 ) to 1 . the high-order 8 bits of output data are set in the high-order pwm register pwmh (address 0035 16 ) and the low-order 6 bits are set in the low-order pwm register pwml (address 0036 16 ). pwm operation the timing of the 14-bit pwm function is shown in figure 65. the 14-bit pwm data is divided into the low-order 6 bits and the high-order 8 bits in the pwm latch. the high-order 8 bits of data determine how long an h level sig- nal is output during each sub-period. there are 64 sub-periods in each period, and each sub-period t is 256 ? (= 64 s) long. the signal s h has a length equal to n times , and its minimum reso- lution = 250 ns. the last bit of the sub-period becomes the add bit which is speci- fied either h or l, by the contents of pwml. as shown in table 11, the add bit is decided either h or l. that is, only in the sub-period tm shown in table 11 in the pwm cycle period t = 64 t, the h duration is lengthened during the minimum resolution width period in comparison with the other period. for example, if the high-order eight bits of the 14-bit data are 03 16 and the low-order six bits are 05 16 , the length of the h level output in sub-periods t8, t24, t32, t40 and t56 is 4 , and its length 3 in all other sub-periods. time at the h level of each sub-period almost becomes equal because the time becomes length set in the high-order 8 bits or becomes the value plus t, and this sub-period t (= 64 s, approxi- mate 15.6 khz) becomes cycle period approximately. table 11 relationship between low-order 6-bit data and setting period of add bit 0 0 0 0 0 0 none 0 0 0 0 0 1 m = 32 0 0 0 0 1 0 m = 16, 48 0 0 0 1 0 0 m = 8, 24, 40, 56 0 0 1 0 0 0 m = 4, 12, 20, 28, 36, 44, 52, 60 0 1 0 0 0 0 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 1 0 0 0 0 0 m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63 lsb sub-periods tm lengthened (m = 0 to 63) low-order 6-bit data transfer from register to latch data written to the pwml register is transferred to the pwm latch once in each pwm period (every 4096 s), and data written to the pwmh register is transferred to the pwm latch once in each sub- period (every 64 s). pulses output from the pwm output pin correspond to this latch contents. when the pwml register is read, the contents of the latch are read. however, bit 7 of the pwml register indicates whether the transfer to the pwm latch is completed: the transfer is completed when bit 7 is 0 , it is not done when bit 7 is 1 . fig. 65 pwm timing
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 64 p 9 6 / p w m 0 o u t p u t s e l e c t i o n b i t 0 : i / o p o r t 1 : p w m 0 o u t p u t n o t u s e d ( r e t u r n 0 w h e n r e a d ) p w m c o n t r o l r e g i s t e r ( p w m c o n : a d d r e s s 0 0 2 6 1 6 ) b 7 b 0 6a 6a 6a 6a 6a 6b 6a 6a 6a 6a 6a 6a 6a 6a 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 a 6 a 6 b 6 b 6 b 6 a 6b 6 b 6 b 6 a 6 b 6 b 6b 6 a 6 a 6 a 6 a 6 a 6a 6a 6 a 6 a 6a 6 a 6 a 6 a 6 a 4 3 4 4 3 4 4 3 4 6 b 6 a 6 9 6 8 6 7 0 2 0 1 6 a 6 9 68 6 7 02 0 1 0 2 0 1 0 0 f f f e f d 9 7 9 6 9 5 02 0 1 00 f c f f f e f d 97 9 6 95 f c a d d a d d 1653 16 1a93 16 1aa4 16 1aa4 16 1ee4 16 1ef5 16 t = 4 0 9 6 s t = 6 4 s 1 3 1 6 a 4 1 6 2 4 1 6 3 5 1 6 7 b 1 6 6 a 1 6 5 9 1 6 data 35 16 stored at address 0036 16 t = 6 4 s = 0.25 s h p e r i o d l e n g t h s p e c i f i e d b y p w m h 1 2 b5 16 2 pwm register ( hi g h-order ) pwm register ( low-order ) pwm latch ( 14-bit ) data 6a 16 stored at address 0035 16 d a t a 2 4 1 6 s t o r e d a t a d d r e s s 0 0 3 6 1 6 bit 7 cleared after transfer transfer from register to latch data 7b 16 stored at address 0035 16 transfer from register to latch w h e n b i t 7 o f p w m l i s 0 , t r a n s f e r f r o m r e g i s t e r t o l a t c h i s d i s a b l e d . pwm output (example 1) low-order 6-bits output h = 6a 16 l = 24 16 6 b 1 6 . . . . . . . . . . . . 3 6 t i m e s ( 1 0 7 ) 6 a 1 6 . . . . . . . . . . . . 2 8 t i m e s ( 1 0 6 ) p w m o u t p u t (example 2) l o w - o r d e r 6 b i t s o u t p u t h = 6 a 1 6 l = 1 8 1 6 6 b 1 6 . . . . . . . . . . . . 2 4 t i m e s6 a 1 6 . . . . . . . . . . . . 4 0 t i m e s pwm output 8 - b i t c o u n t e r t h e a d d p o r t i o n s w i t h a d d i t i o n a l a r e d e t e r m i n e d e i t h e r h o r l b y l o w - o r d e r 6 - b i t d a t a . m i n i m u m b i t w i d t h ( 6 4 6 4 s ) ? 1 0 6 ? 6 4 2 4 (256 0.25 s) 2 5 6 ( 6 4 s ) , f i x e d 1 0 6 ? 6 4 3 6 ? fig. 67 14-bit pwm timing fig. 66 structure of pwm control register
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 65 f ( x i n ) / 1 2 8 f ( x c i n ) 1 / 4 1 / 2 1 / 1 f ( x c i n ) c o u n t e r s a m p l i n g c l o c k s e l e c t i o n b i t i n t 2 i n t e r r u p t i n p u t n o i s e f i l t e r 8 - b i t b i n a r y u p c o u n t e r i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n r e g i s t e r a d d r e s s 0 0 3 0 1 6 d a t a b u s d i v i d e r o n e - s i d e d / b o t h - s i d e d e d g e d e t e c t i o n s e l e c t i o n b i t n o i s e f i l t e r s a m p l i n g c l o c k s e l e c t i o n b i t c o u n t e r o v e r f l o w i n t e r r u p t r e q u e s t o r r e m o t e c o n t r o l i n t e r r u p t r e q u e s t d i v i d e r 1 / 1 1 / 2 f ( x i n ) / 3 2 i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t interrupt interval determination function the 38b7 group has an interrupt interval determination circuit. this interrupt interval determination circuit has an 8-bit binary up counter. using this counter, it determines a duration of time from the rising edge (falling edge) of an input signal pulse on the p7 2 / int 2 pin to the rising edge (falling edge) of the signal pulse that is input next. how to determine the interrupt interval is described below. 1. enable the int 2 interrupt by setting bit 2 of the interrupt control register 1 (address 003e 16 ). select the rising interval or falling interval by setting bit 2 of the interrupt edge selection register (address 003a 16 ). 2. set bit 0 of the interrupt interval determination control register (address 0031 16 ) to 1 (interrupt interval determination operat- ing). 3. select the sampling clock of 8-bit binary up counter by setting bit 1 of the interrupt interval determination control register. 4. when the signal of polarity which is set on the int 2 pin (rising or falling edge) is input, the 8-bit binary up counter starts count- ing up of the selected counter sampling clock. 5. when the signal of polarity selected above is input again, the value of the 8-bit binary up counter is transferred to the inter- rupt interval determination register (address 0030 16 ), and the remote control interrupt request occurs. immediately after that, the 8-bit binary up counter continues to count up again from 00 16 . 6. when count value reaches ff 16 , the 8-bit binary up counter stops counting up. then, simultaneously when the next counter sampling clock is input, the counter sets value ff 16 to the in- terrupt interval determination register to generate the counter overflow interrupt request. fig. 68 interrupt interval determination circuit block diagram noise filter the p7 2 /int 2 pin builds in the noise filter. the noise filter operation is described below. 1. select the sampling clock of the input signal with bits 2 and 3 of the interrupt interval determination control register. when not using the noise filter, set 00 16 . 2. the p7 2 /int 2 input signal is sampled in synchronization with the selected clock. when sampling the same level signal in a series of three sampling, the signal is recognized as the inter- rupt signal, and the interrupt request occurs. when setting bit 4 of interrupt interval determination control regis- ter to 1 , the interrupt request can occur at both rising and falling edges. when using the noise filter, set the minimum pulse width of the int 2 input signal to 3 cycles or more of the sample clock.
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 66 i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n c o n t r o l r e g i s t e r ( i i d c o n : a d d r e s s 0 0 3 1 1 6 ) i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n c i r c u i t o p e r a t i n g s e l e c t i o n b i t 0 : s t o p p e d 1 : o p e r a t i n g c o u n t e r s a m p l i n g c l o c k s e l e c t i o n b i t 0 : f ( x i n ) / 1 2 8 o r f ( x c i n ) 1 : f ( x i n ) / 2 5 6 o r f ( x c i n ) / 2 n o i s e f i l t e r s a m p l i n g c l o c k s e l e c t i o n b i t s ( i n t 2 ) b 3 b 2 0 0 : f i l t e r s t o p 0 1 : f ( x i n ) / 3 2 o r f ( x c i n ) 1 0 : f ( x i n ) / 6 4 o r f ( x c i n ) / 2 1 1 : f ( x i n ) / 1 2 8 o r f ( x c i n ) / 4 o n e - s i d e d / b o t h - s i d e d e d g e d e t e c t i o n s e l e c t i o n b i t 0 : o n e - s i d e d e d g e d e t e c t i o n 1 : b o t h - s i d e d e d g e d e t e c t i o n ( c a n b e u s e d w h e n u s i n g a n o i s e f i l t e r ) n o t u s e d ( r e t u r n 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h e s e b i t s . ) b 7 b 0 remote control interru p t re q uest 0 1 2 3 4 5 6 1 2 3 0 fe f f n f f 0 f f 6 6 n 1 n ( w h e n i i d c o n 4 = 0 ) n o i s e f i l t e r s a m p l i n g c l o c k i n t 2 p i n acceptance of interru p t counter sampling clock 8 - b i t b i n a r y u p c o u n t e r v a l u e i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n r e g i s t e r v a l u e remote control interru p t re q uest c o u n t e r o v e r f l o w i n t e r r u p t r e q u e s t 0 1 1 0 f e f f 2 f f 2 3 3 f f 2 n n n 3 2 2 2 0 1 2 1 0 1 0 2 r e m o t e c o n t r o l i n t e r r u p t r e q u e s t ( w h e n i i d c o n 4 = 1 ) n o i s e f i l t e r s a m p l i n g c l o c k i n t 2 p i n a c c e p t a n c e o f i n t e r r u p t c o u n t e r s a m p l i n g c l o c k 8 - b i t b i n a r y u p c o u n t e r v a l u e i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n r e g i s t e r v a l u e r e m o t e c o n t r o l i n t e r r u p t r e q u e s t c o u n t e r o v e r f l o w i n t e r r u p t r e q u e s t r e m o t e c o n t r o l i n t e r r u p t r e q u e s t r e m o t e c o n t r o l i n t e r r u p t r e q u e s t fig. 71 interrupt interval determination operation example (at both-sided edge active) fig. 70 interrupt interval determination operation example (at rising edge active) fig. 69 structure of interrupt interval determination control register
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 67 x in data bus x cin 1 0 internal system clock selection bit (note) 0 1 1/8 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) ff 16 is set when watchdog timer control register is written to. internal reset reset watchdog timer l (8) note: either high-speed, middle-speed or low-speed mode is selected by bit 7 of cpu mode register. stp instruction ff 16 is set when watchdog timer control register is written to. 1/2 (2) watchdog timer h count source selection bit operation bit 7 of the watchdog timer control register (address 0eee 16 ) per- mits selecting a watchdog timer h count source. when this bit is set to 0 , the underflow signal of watchdog timer l becomes the count source. the detection time is set to 131.072 ms at f(x in ) = 4 mhz frequency, and 32.768 s at f(x cin ) = 32 khz frequency. when this bit is set to 1 , the count source becomes the signal di- vided by 8 for f(x in ) or divided by 16 for f(x cin ). the detection time in this case is set to 512 s at f(x in ) = 4 mhz frequency, and 128 ms at f(x cin ) = 32 khz frequency. this bit is cleared to 0 after reset. (3) operation of stp instruction disable bit bit 6 of the watchdog timer control register (address 0eee 16 ) per- mits disabling the stp instruction when the watchdog timer is in operation. when this bit is 0 , the stp instruction is enabled. when this bit is 1 , the stp instruction is disabled. if the stp instruction is executed, an internal resetting occurs. when this bit is set to 1 , it cannot be rewritten to 0 by program. this bit is cleared to 0 after reset. note when releasing the stop mode, the watchdog timer performs its count operation even in the stop release waiting time. be careful not to cause the watchdog timer h to underflow in the stop release waiting time, for example, by writing any data in the watchdog timer control register (address 0eee 16 ) before executing the stp instruction. watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software runaway). the watchdog timer consists of an 8-bit watchdog timer l and a 8-bit watchdog timer h. standard operation of watchdog timer when any data is not written into the watchdog timer control reg- ister (address 0eee 16 ) after reset, the watchdog timer is in the stop state. the watchdog timer starts to count down by writing an optional value into the watchdog timer control register and an in- ternal reset occurs at an underflow of the watchdog timer h. accordingly, programming is usually performed so that writing to the watchdog timer control register may be started before an un- derflow. when the watchdog timer control register is read, the values of the high-order 6 bits of the watchdog timer h, stp in- struction disable bit, and watchdog timer h count source selection bit are read. (1) initial value of watchdog timer at reset or writing to the watchdog timer control register (address 0eee 16 ), a watchdog timer h is set to ff 16 and a watchdog timer l to ff 16 . fig. 73 structure of watchdog timer control register fig. 72 block diagram of watchdog timer b0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/8 or f(x cin )/16 watchdog timer h (for read-out of high-order 6 bits) watchdog timer control register (wdtcon : address 0eee 16 ) b7
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 68 buzzer output circuit the 38b7 group has a buzzer output circuit. one of 1 khz, 2 khz and 4 khz (at x in = 4.19 mhz) frequencies can be selected by the buzzer output control register (address 0efd 16 ). either p7 7 /b uz01 or p9 7 /b uz02 /an 15 can be selected as a buzzer output port by the output port selection bits (b2 and b3 of address 0efd 16 ). the buzzer output is controlled by the buzzer output on/off bit (b4). fig. 74 block diagram of buzzer output circuit fig. 75 structure of buzzer output control register note: in the low-speed mode, a buzzer output is made off. f(x in ) 1/1024 1/2048 1/4096 port latch buzzer output buzzer output on/off bit output port control signal port direction register divider buzzer output control register (buzcon: address 0efd 16 ) output frequency selection bits (x in = 4.19 mhz) b1b0 0 0 : 1 khz (f(x in )/4096) 0 1 : 2 khz (f(x in )/2048) 1 0 : 4 khz (f(x in )/1024) 1 1 : not available output port selection bits b3b2 0 0 : p7 7 and p9 7 function as ordinary ports. 0 1 : p7 7 /b uz01 functions as a buzzer output. 1 0 : p9 7 /b uz02 /an 15 functions as a buzzer output. 1 1 : not available buzzer output on/off bit b4 0 : buzzer output off ( 0 output) 1 : buzzer output on not used (returns 0 when read) b7 b0
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 69 reset circuit to reset the microcomputer, reset pin should be held at an l level for 2 s or more. then the reset pin is returned to an h level (the power source voltage should be between 2.7 v and 5.5 v, and the oscillation should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low- order byte). make sure that the reset input voltage is less than 0.54 v for vcc of 2.7 v (switching to the high-speed mode, a power source voltage must be between 4.0 v and 5.5 v). fig. 77 reset sequence fig. 76 reset circuit example (note) 0.2v cc 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; vcc=2.7 v reset internal reset data address sync x in : about 4000 cycles x in ? ? ? ? ? fffc fffd ad h , ad l 1 : the frequency relation of f(x in ) and f( ) is f(x in )=4 f( ). 2 : the question marks (?) indicate an undefined state that depends on the previous state. notes ad l ad h
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 70 fig. 78 internal status at reset 0 0 1 6 0 0 1 6 3 f 1 6 f f 1 6 f f 1 6 0 0 2 b 1 6 0 e e e 1 6 0 0 2 c 1 6 0 0 2 d 1 6 0 0 2 e 1 6 0 0 2 f 1 6 0 0 3 2 1 6 ? : n o t f i x e d s i n c e t h e i n i t i a l v a l u e s f o r o t h e r t h a n a b o v e m e n t i o n e d r e g i s t e r s a n d r a m c o n t e n t s a r e i n d e f i n i t e a t r e s e t , t h e y m u s t b e s e t . a d d r e s s r e g i s t e r c o n t e n t s a d d r e s s r e g i s t e r c o n t e n t s 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 f f 1 6 f f 1 6 f f 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 0 0 1 6 0 0 0 2 1 6 0 0 0 4 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 3 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 8 1 6 t i m e r 4 p o r t p 0 p o r t p 1 p o r t p 2 p o r t p 3 p o r t p 3 d i r e c t i o n r e g i s t e r p o r t p 4 p o r t p 4 d i r e c t i o n r e g i s t e r p o r t p 5 p o r t p 5 d i r e c t i o n r e g i s t e r p o r t p 6 p o r t p 6 d i r e c t i o n r e g i s t e r p o r t p 7 p o r t p 7 d i r e c t i o n r e g i s t e r p o r t p 8 p o r t p 8 d i r e c t i o n r e g i s t e r u a r t c o n t r o l r e g i s t e r s e r i a l i / o 1 c o n t r o l r e g i s t e r 1 s e r i a l i / o 1 c o n t r o l r e g i s t e r 2 s e r i a l i / o 1 c o n t r o l r e g i s t e r 3 s e r i a l i / o 2 c o n t r o l r e g i s t e r s e r i a l i / o 2 s t a t u s r e g i s t e r t i m e r 1 t i m e r 2 t i m e r 3 t i m e r 5 t i m e r 6 p w m c o n t r o l r e g i s t e r t i m e r 1 2 m o d e r e g i s t e r ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 1 0 ) ( 1 1 ) ( 1 2 ) ( 1 3 ) ( 1 4 ) ( 1 5 ) ( 1 6 ) ( 1 7 ) ( 1 8 ) ( 1 9 ) ( 2 0 ) ( 2 1 ) ( 2 2 ) ( 2 3 ) ( 2 4 ) ( 2 5 ) ( 2 6 ) ( 2 7 ) ( 2 8 ) ( 2 9 ) ( 3 0 ) ( 3 1 ) ( 3 2 ) 0 0 1 6 0 0 2 9 1 6 t i m e r 3 4 m o d e r e g i s t e r ( 3 3 ) ( 3 9 ) ( 4 0 ) ( 4 1 ) ( 4 2 ) ( 5 5 ) ( 4 4 ) ( 4 5 ) d - a c o n v e r s i o n r e g i s t e r w a t c h d o g t i m e r c o n t r o l r e g i s t e r t i m e r x ( l o w - o r d e r ) t i m e r x ( h i g h - o r d e r ) t i m e r x m o d e r e g i s t e r 1 t i m e r x m o d e r e g i s t e r 2 i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n c o n t r o l r e g i s t e r a d / d a c o n t r o l r e g i s t e r 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 f f 1 6 0 0 1 6 0 0 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 0 e f 0 1 6 0 e f 1 1 6 0 e f 2 1 6 0 e f 3 1 6 0 e f 4 1 6 0 e f 5 1 6 0 e f 6 1 6 0 e f 7 1 6 0 e f 9 1 6 0 e f a 1 6 0 e f b 1 6 0 e f c 1 6 0 e f d 1 6 ( 4 7 ) ( 4 8 ) ( 4 9 ) ( 5 0 ) ( 5 1 ) ( 5 2 ) ( 5 3 ) ( 5 4 ) ( 5 6 ) ( 5 9 ) ( 6 0 ) ( 6 1 ) ( 6 2 ) ( 6 3 ) ( 6 4 ) ( 6 5 ) ( 6 6 ) ( 6 7 ) ( 6 8 ) f l d o u t p u t c o n t r o l r e g i s t e r f l d c m o d e r e g i s t e r i n t e r r u p t s o u r c e s w i t c h r e g i s t e r i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r c p u m o d e r e g i s t e r i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t e r r u p t r e q u e s t r e g i s t e r 2 i n t e r r u p t c o n t r o l r e g i s t e r 1 i n t e r r u p t c o n t r o l r e g i s t e r 2 p u l l - u p c o n t r o l r e g i s t e r 1 p u l l - u p c o n t r o l r e g i s t e r 2 p o r t p 0 d i g i t o u t p u t s e t s w i t c h r e g i s t e r t d i s p t i m e s e t r e g i s t e r t o f f 1 t i m e s e t r e g i s t e r t o f f 2 t i m e s e t r e g i s t e r p o r t p 4 f l d / p o r t s w i t c h r e g i s t e r p o r t p 5 f l d / p o r t s w i t c h r e g i s t e r p o r t p 6 f l d / p o r t s w i t c h r e g i s t e r f f 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 1 0 1 6 p o r t p 9 p o r t p 9 d i r e c t i o n r e g i s t e r ( 3 8 ) f f f c 1 6 c o n t e n t s ( p s ) ( p c h ) ( p c l ) ( 6 9 ) ( 7 2 ) ( 7 3 ) p r o g r a m c o u n t e r b u z z e r o u t p u t c o n t r o l r e g i s t e r p r o c e s s o r s t a t u s r e g i s t e r f f f d 1 6 c o n t e n t s 1 ? 0 0 3 1 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 8 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 8 0 1 6 f f 1 6 0 1 1 6 f f 1 6 010010 0 0 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 ? ? ? ?? ? 0 0 1 6 0 0 0 3 1 6 p o r t p 1 d i r e c t i o n r e g i s t e r 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 p o r t p a p o r t p a d i r e c t i o n r e g i s t e r p o r t p b p o r t p b d i r e c t i o n r e g i s t e r 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 ( 3 4 ) ( 3 5 ) ( 3 6 ) ( 4 3 ) i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n r e g i s t e r 0 0 3 0 1 6 0 0 1 6 ( 4 6 ) 0 e e c 1 6 s e r i a l i / o 3 c o n t r o l r e g i s t e r 0 0 1 6 0 e e f 1 6 p u l l - u p c o n t r o l r e g i s t e r 3 0 0 1 6 ( 5 7 ) ( 5 8 ) p o r t p 2 d i g i t o u t p u t s e t s w i t c h r e g i s t e r 0 e f e 1 6 ( 7 0 ) f l a s h m e m o r y c o n t r o l r e g i s t e r 0 0 1 6 0 e f f 1 6 ( 7 1 ) f l a s h c o m m a n d r e g i s t e r 0 0 1 6 0 0 2 a 1 6 t i m e r 5 6 m o d e r e g i s t e r ( 3 7 ) 0 0 1 6
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 71 clock generating circuit the 38b7 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out or x cin and x cout . use the circuit constants in accordance with the resonator manufacturer s recommended values. no exter- nal resistor is needed between x in and x out since a feedback resistor exists on-chip. however, an external feedback resistor is needed between x cin and x cout . immediately after power on, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal system clock is the frequency of x in divided by 4. af- ter reset, this mode is selected. (2) high-speed mode the internal system clock is the frequency of x in . (3) low-speed mode the internal system clock is the frequency of x cin divided by 2. note if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub clock to stabilize, especially immediately af- ter power on and at returning from stop mode. when switching the mode between middle/high-speed and low-speed, set the fre- quency on condition that f(x in ) > 3 f(x cin ). (4) low power consumption mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set the main clock stop bit (bit 5) of the cpu mode register to 1 . when the main clock x in is restarted (by setting the main clock stop bit to 0 ), set enough time for oscillation to stabilize. oscillation control (1) stop mode if the stp instruction is executed, the internal system clock stops at an h level, and x in and x cin oscillators stop. timer 1 is set to ff 16 and timer 2 is set to 01 16 . either x in divided by 8 or x cin divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. the bits of the timer 12 mode register are cleared to 0 . set the interrupt enable bits of the timer 1 and timer 2 to disabled ( 0 ) be- fore executing the stp instruction. oscillator restarts when an external interrupt is received, but the internal system clock is not supplied to the cpu until timer 2 underflows. this allows time for the clock circuit oscillation to stabilize. (2) wait mode if the wit instruction is executed, the internal system clock stops at an h level. the states of x in and x cin are the same as the state before executing the wit instruction. the internal system clock restarts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immedi- ately after the clock is restarted. fig. 79 ceramic resonator circuit fig. 80 external clock input circuit x cin x cout x in x out c in c out c cin c cout rf rd x in x out external oscillation circuit v cc v ss open x cin x cout external oscillation circuit or external pulse open v cc v ss
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 72 wit instruction stp instruction timing (internal clock) s r q stp instruction s r q main clock stop bit ( note 3 ) s r q 1/4 x in x out x cout x cin interrupt request reset interrupt disable flag l 1/2 1/2 port x c switch bit ( note 3 ) 1 0 1 timer 1 count source selection bit ( note 2 ) low-speed mode high-speed or middle-speed mode middle-speed mode high-speed or low-speed mode internal system clock selection bit ( notes 1, 3 ) 1 0 timer 1 timer 2 timer 2 count source selection bit ( note 2 ) 0 main clock division ratio selection bits ( note 3 ) 1 0 1 0 notes 1: when low-speed mode is selected, set the port xc switch bit (b4) to 1 . 2: refer to the structure of the timer 12 mode register. 3: refer to the structure of the cpu mode register. fig. 81 clock generating circuit block diagram
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 73 c m 4 : p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n 1 : x c i n - x c o u t o s c i l l a t i n g f u n c t i o n c m 5 : m a i n c l o c k ( x i n - x o u t ) s t o p b i t 0 : o s c i l l a t i n g 1 : s t o p p e d c m 6 : m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t 0 : f ( x i n ) ( h i g h - s p e e d m o d e ) 1 : f ( x i n ) / 4 ( m i d d l e - s p e e d m o d e ) c m 7 : i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t 0 : x i n x o u t s e l e c t e d ( m i d d l e - / h i g h - s p e e d m o d e ) 1 : x c i n x c o u t s e l e c t e d ( l o w - s p e e d m o d e ) r e s e t c m 4 c m 7 c m 4 c m 5 c m 6 c m 6 c p u m o d e r e g i s t e r ( c p u m : a d d r e s s 0 0 3 b 1 6 ) b 7b 4 c m 7 c m 5 c m 6 c m 6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 c m 4 1 0 c m 4 0 1 0 1 c m 5 1 0 0 1 c m 5 0 1 0 1 0 1 c m 6 c m 6 c m 6 c m 6 c m 7 = 0 ( 4 m h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) 1 : s w i t c h t h e m o d e b y t h e a l l o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( d o n o t s w i t c h b e t w e e n t h e m o d e d i r e c t l y w i t h o u t a n a l l o w . ) 2 : t h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d . 3 : t i m e r o p e r a t e s i n t h e w a i t m o d e . 4 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 1 m s o c c u r s b y t i m e r 1 i n m i d d l e - / h i g h - s p e e d m o d e . 5 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 0 . 2 5 s o c c u r s b y t i m e r 1 i n l o w - s p e e d m o d e . 6 : t h e e x a m p l e a s s u m e s t h a t 4 m h z i s b e i n g a p p l i e d t o t h e x i n p i n a n d 3 2 k h z t o t h e x c i n p i n . i n d i c a t e s t h e i n t e r n a l s y s t e m c l o c k . m i d d l e - s p e e d m o d e ( = 1 m h z ) m i d d l e - s p e e d m o d e ( = 1 m h z ) c m 7 = 0 ( 4 m h z s e l e c t e d ) c m 6 = 0 ( h i g h - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) h i g h - s p e e d m o d e ( = 4 m h z ) c m 7 = 0 ( 4 m h z s e l e c t e d ) c m 6 = 0 ( h i g h - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) h i g h - s p e e d m o d e ( = 4 m h z ) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 0 ( h i g h - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - s p e e d m o d e ( = 1 6 k h z ) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 0 ( h i g h - s p e e d ) c m 5 = 1 ( x i n s t o p p e d ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) c m 7 = 0 ( 4 m h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - s p e e d m o d e ( = 1 6 k h z ) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 1 ( x i n s t o p p e d ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - p o w e r d i s s i p a t i o n m o d e ( = 1 6 k h z ) l o w - p o w e r d i s s i p a t i o n m o d e ( = 1 6 k h z ) n o t e s fig. 82 state transitions of system clock
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 74 mask option of pull-down resistor (object product: mask rom version) whether built-in pull-down resistors are connected or not to high- breakdown voltage ports p4 0 to p4 7 , p5 0 to p5 7 , and p6 0 to p6 3 can be specified in ordering mask rom. the option type can be specified from among 7 types; a to g. notes 1: the electrical characteristics of high-breakdown voltage ports p4 0 to p4 7 , p5 0 to p5 7 , and p6 0 to p6 3 s built-in pull-down resistors are the same as that of high-breakdown voltage ports p0 0 to p0 7 . 2: the absolute maximum ratings of power dissipation may be exceed owing to the number of built-in pull-down resistor. after calcu - lating the power dissipation, specify the option type. 3: the flash memory version cannot select whether built-in pull-down resistors are connected or not. this is the same as option t ype a. power dissipation calculating method (fixed number depending on microcomputers standard) v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma resistor value = 48 k ? (min.) power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v ? 15 ma = 75 mw ( fixed number depending on use condition) apply voltage to v ee pin: vcc 45 v timing number a; digit number b; segment number c ratio of toff time corresponding tdisp time: 1/16 turn on segment number during repeat cycle: d all segment number during repeat cycle: e (= a ? c) total number of built-in resistor: for digit, f; for segment, g digit pin current value h (ma) segment pin current value i (ma) a b c d e f g p4 0 p4 1 p4 2 p4 3 p4 4 p4 5 p4 6 p4 7 p5 0 p5 1 p5 2 p5 3 p5 4 p5 5 p5 6 p5 7 p6 0 p6 1 p6 2 0000000000000000000 p6 3 0 1111000000000000000 0 1111111100000000000 0 1111111111110000000 0 1111111111111111000 0 1111111111111111110 0 1111111111111111111 1 (1) digit pin power dissipation {h ? b ? (1 toff / tdisp) ? voltage} / a (2) segment pin power dissipation {i ? d ? (1 toff / tdisp) ? voltage} / a (3) pull-down resistor power dissipation (digit) {power dissipation per 1 digit ? (b ? f / b) ? (1 toff / tdisp) } / a (4) pull-down resistor power dissipation (segment) {power dissipation per 1 segment ? (d ? g / c) ? (1 toff / tdisp) } / a (5) internal circuit power dissipation (cpu, rom, ram etc.) = 190 mw (1) + (2)+ (3) + (4) + (5) = x mw
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 75 fig. 83 digit timing waveform (1) power dissipation calculating example 1 (fixed number depending on microcomputer s standard) v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma resistor value 43 v / 900 s = 48 k ? (min.) power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v ? 15 ma = 75 mw ( fixed number depending on use condition) apply voltage to v ee pin: vcc 45 v timing number 17; digit number 16; segment number 20 ratio of toff time corresponding tdisp time: 1/16 turn on segment number during repeat cycle: 31 all segment number during repeat cycle: 340 (= 17 ? 20) total number of built-in resistor: for digit, 16; for segment, 20 digit pin current value 18 (ma) segment pin current value 3 (ma) (1) digit pin power dissipation {18 ? 16 ? (1 1 / 16) ? 2} / 17 = 31.77 mw (2) segment pin power dissipation {3 ? 31 ? (1 1 / 16) ? 2} / 17 = 10.26 mw (3) pull-down resistor power dissipation (digit) [{45 2} 2 / 48 ? (16 ? 16 / 16) ? (1 1 / 16)] / 17 = 33.94 mw (4) pull-down resistor power dissipation (segment) [{45 2} 2 / 48 ? (31 ? 20 / 20) ? (1 1 / 16)] / 17 = 65.86 mw (5) internal circuit power dissipation (cpu, rom, ram etc.) = 75 mw (1) + (2)+ (3) + (4) + (5) = 217 mw dig0 dig1 dig2 dig3 dig13 dig14 dig15 timing number 12 3 16 17 15 14 tscan repeat cycle
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 76 power dissipation calculating example 2 (2 or more digits turned on at the same time) (fixed number depending on microcomputer s standard) v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma resistor value 43 v / 900 s = 48 k ? (min.) power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v ? 15 ma = 75 mw ( fixed number depending on use condition) apply voltage to v ee pin: vcc 45 v timing number 11; digit number 12; segment number 24 ratio of toff time corresponding tdisp time: 1/16 turn on segment number during repeat cycle: 114 all segment number during repeat cycle: 264 (= 11 ? 24) total number of built-in resistor: for digit, 10; for segment, 22 digit pin current value 18 (ma) segment pin current value 3 (ma) (1) digit pin power dissipation {18 ? 12 ? (1 1 / 16) ? 2} / 11 = 36.82 mw (2) segment pin power dissipation {3 ? 114 ? (1 1 / 16) ? 2} / 11 = 58.30 mw (3) pull-down resistor power dissipation (digit) [{45 2} 2 / 48 ? (12 ? 10 / 12) ? (1 1 / 16)] / 11 = 32.84 mw (4) pull-down resistor power dissipation (segment) [{45 2} 2 / 48 ? (114 ? 22 / 24) ? (1 1 / 16)] / 11 = 343.08 mw (5) internal circuit power dissipation (cpu, rom, ram etc.) = 75 mw (1) + (2)+ (3) + (4) + (5) = 547 mw dig0 dig1 dig2 dig3 dig7 dig8 dig9 timing number 12 3 45 6 7 89 1011 dig4 dig5 dig6 tscan repeat cycle fig. 84 digit timing waveform (2)
77 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. flash memory mode the M38B79ff has the flash memory mode in addition to the nor- mal operation mode (microcomputer mode). the user can use this mode to perform read, program, and erase operations for the in- ternal flash memory. the M38B79ff has three modes the user can choose: the paral- lel input/output and serial input/output mode, where the flash memory is handled by using the external programmer, and the cpu reprogramming mode, where the flash memory is handled by the central processing unit (cpu). the following explains these modes. (1) flash memory mode 1 (parallel i/o mode) the parallel i/o mode can be selected by connecting wires as shown in figures 85 and supplying power to the v cc and v pp pins. in this mode, the M38B79ff operates as an equivalent of mitsubishis cmos flash memory m5m28f101. however, be- cause the M38B79ffs internal memory has a capacity of 60 kbytes, programming is available for addresses 01000 16 to 0ffff 16 , and make sure that the data in addresses 00000 16 to 00fff 16 and addresses 10000 16 to 1ffff 16 are ff 16 . note also that the M38B79ff does not contain a facility to read out a device identification code by applying a high voltage to address input (a 9 ). be careful not to erratically set program conditions when us- ing a general-purpose prom programmer. table 12 shows the pin assignments when operating in the paral- lel input/output mode. table 12 pin assignments of M38B79ff when operating in the parallel input/output mode v cc v pp v ss address input data i/o __ ce ___ oe ___ we M38B79ff v cc cnv ss v ss ports p0, p1, p3 1 port p2 p3 6 p3 7 p3 3 m5m28f101 v cc v pp v ss a 0 ? 16 d 0 ? 7 __ ce __ oe ___ we functional outline (parallel input/output mode) in the parallel input/output mode, the M38B79ff allow the user to choose an operation mode between the read-only mode and the read/write mode (software command control mode) depending on the voltage applied to the v pp pin. when v pp = v pp l, the read- only mode is selected, and the user can choose one of three states (e.g., read, output disable, or standby) depending on inputs ___ ___ ___ to the ce, oe, and we pins. when v pp = v pp h, the read/write mode is selected, and the user can choose one of four states (e.g., read, output disable, standby, or write) depending on inputs __ __ ___ to the ce, oe, and we pins. table 13 shows assignment states of control input and each state. read __ the microcomputer enters the read state by driving the ce, and __ ___ oe pins low and the we pin high; and the contents of memory corresponding to the address to be input to address input pins (a 0 ? 16 ) are output to the data input/output pins (d 0 ? 7 ). output disable the microcomputer enters the output disable state by driving the __ ___ __ ce pin low and the we and oe pins high; and the data input/out- put pins enter the floating state. standby __ the microcomputer enters the standby state by driving the ce pin high. the M38B79ff is placed in a power-down state consuming only a minimal supply current. at this time, the data input/output pins enter the floating state. write the microcomputer enters the write state by driving the v pp pin ___ __ high (v pp = v pp h) and then the we pin low when the ce pin is __ low and the oe pin is high. in this state, software commands can be input from the data input/output pins, and the user can choose program or erase operation depending on the contents of this soft- ware command. pin mode read output disable standby read output disable standby write read-only read/write __ ce v il v il v ih v il v il v ih v il v il v ih v il v ih v ih table 13 assignment states of control input and each state __ oe ___ we v ih v ih v ih v ih v il v pp l v pp l v pp l v pp h v pp h v pp h v pp h v pp output floating floating output floating floating input data i/o note: can be v il or v ih . state
78 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. supply 5 v ?10 % to v cc and 0 v to v ss . connect to 5 v ?10 % in read-only mode, connect to 11.7 v to 12.6 v in read/write mode. connect to v ss . connect a ceramic resonator between x in and x out . connect to v ss . connect to v ss . port p0 functions as 8-bit address input (a 0 ? 7 ). port p1 functions as 8-bit address input (a 8 ? 15 ). function as 8-bit datas i/o pins (d 0 ? 7 ). connect them to vss through each resistor of 6.8 k ?. p3 7 , p3 6 and p3 3 function as the oe, ce and we input pins respectively. p3 1 functions as the a 16 input pin. connect p3 0 and p3 2 to v ss . input ? or ? to p3 4 , p3 5 , or keep them open. input ??or ?? or keep them open. input ??or ?? or keep them open. connect p6 4 and p6 6 to v ss . input ??or ??to p6 0 ?6 3 , p6 5 , p6 7 , or keep them open. input ??or ?? or keep them open. input ??or ?? or keep them open. input ??or ?? or keep them open. input ??or ?? or keep them open. input ??or ?? or keep them open. keep this open. power supply v pp input reset input clock input clock output analog supply input reference voltage input address input (a 0 ? 7 ) address input (a 8 ? 15 ) data i/o (d 0 ? 7 ) control signal input input port p4 input port p5 input port p6 input port p7 input port p8 input port p9 input port pa input port pb pull-down power supply table 14 pin description (flash memory parallel i/o mode) pin name input input input output input input input i/o input input input input input input input input input input /output functions v cc , v ss cnv ss reset x in x out av ss v ref p0 0 ?0 7 p1 0 ?1 7 p2 0 ?2 7 p3 0 ?3 7 p4 0 ?4 7 p5 0 ?5 7 p6 0 ?6 7 p7 0 ?7 7 p8 0 ?8 3 p9 0 ?9 7 pa 0 ?a 7 pb 0 ?b 6 v ee
79 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 85 pin connection of M38B79ff when operating in parallel input/output mode 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 38 39 40 41 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 81 82 8 3 84 85 86 8 7 8 8 8 9 9 0 9 1 9 2 9 3 94 95 96 9 7 9 8 9 9 1 0 0 m 3 8 b 7 9 f f f p * p 4 7 / f l d 3 9 * p 0 0 / f l d 8 * p 0 3 / f l d 1 1 * p 0 4 / f l d 1 2 * p 0 5 / f l d 1 3 * p 0 6 / f l d 1 4 * p 0 7 / f l d 1 5 * p 1 1 / f l d 1 7 * p 1 2 / f l d 1 8 * p 1 3 / f l d 1 9 * p 1 4 / f l d 2 0 * p 1 5 / f l d 2 1 * p 1 6 / f l d 2 2 * p 1 7 / f l d 2 3 * p 1 0 / f l d 1 6 * p 0 1 / f l d 9 * p 0 2 / f l d 1 0 v e e * p 4 6 / f l d 3 8 * p 4 3 / f l d 3 5 * p 4 2 / f l d 3 4 * p 4 1 / f l d 3 3 * p 4 0 / f l d 3 2 * p 3 7 / f l d 3 1 * p 3 6 / f l d 3 0 * p 3 5 / f l d 2 9 * p 3 4 / f l d 2 8 * p 3 3 / f l d 2 7 * p 3 2 / f l d 2 6 * p 3 1 / f l d 2 5 * p 3 0 / f l d 2 4 * p 4 5 / f l d 3 7 * p 4 4 / f l d 3 6 p b 5 / s o u t 1 p b 4 / s c l k 1 1 p b 3 / s s t b 1 p a 6 / a n 6 p a 7 / a n 7 v ref av ss p 9 0 / s i n 3 / a n 8 p 9 1 / s o u t 3 / a n 9 p 9 2 / s c l k 3 / a n 1 0 p 9 4 / r t p 1 / a n 1 2 p 9 5 / r t p 0 / a n 1 3 p 9 6 / p w m 0 / a n 1 4 p 9 7 / b u z 0 2 / a n 1 5 p b 2 / s b u s y 1 p a 1 / a n 1 p a 0 / a n 0 p 8 1 / x c o u t p 8 0 / x c i n p 7 4 / p w m 1 p 7 3 / i n t 3 / d i m o u t p 7 2 / i n t 2 p7 1 /int 1 p7 0 /int 0 p a 5 / a n 5 pb 0 /s clk12 /sv in /da pb 1 /s rdy1 p 7 5 / t 1 o u t x i n x o u t v c c p 7 6 / t 3 o u t v s s p 7 7 / i n t 4 / b u z 0 1 r e s e t p a 4 / a n 4 p a 3 / a n 3 p a 2 / a n 2 *p2 0 /fld 0 *p2 1 /fld 1 *p2 2 /fld 2 * p 2 3 / f l d 3 * p 2 4 / f l d 4 * p 2 5 / f l d 5 *p2 6 /fld 6 * p 2 7 / f l d 7 p b 6 / s i n 1 * p 5 1 / f l d 4 1 * p 5 0 / f l d 4 0 * p 5 3 / f l d 4 3 * p 5 2 / f l d 4 2 * p 5 5 / f l d 4 5 * p 5 4 / f l d 4 4 *p5 7 /fld 47 * p 5 6 / f l d 4 6 *p6 1 /fld 49 *p6 0 /fld 48 * p 6 3 / f l d 5 1 * p 6 2 / f l d 5 0 p6 5 /txd/fld 53 p 6 4 / r x d / f l d 5 2 p 6 7 / s r d y 2 / s c l k 2 2 / f l d 5 5 p6 6 /s clk21 /fld 54 p 8 2 / c n t r 1 c n v s s p 8 3 / c n t r 0 / c n t r 2 p 9 3 / s r d y 3 / a n 1 1 a 1 6 w e a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 5 o e c e v p p v c c d 7 d 6 d 5 d 4 d3 d 2 d1 d0 v s s 6 . 8 k ? ? : c o n n e c t t o t h e c e r a m i c o s c i l l a t i o n c i r c u i t . : h i g h - b r e a k d o w n - v o l t a g e o u t p u t p o r t : t o t a l i n g 5 2 i n d i c a t e s t h e f l a s h m e m o r y p i n . * ? package type: 100p6s-a
80 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. read-only mode the microcomputer enters the read-only mode by applying v pp l to the v pp pin. in this mode, the user can input the address of a memory location to be read and the control signals at the timing shown in figure 86, and the M38B79ff will output the contents of the user s specified address from data i/o pin to the external. in this mode, the user cannot perform any operation other than read. fig. 86 read timing read/write mode the microcomputer enters the read/write mode by applying v pp h to the v pp pin. in this mode, the user must first input a software command to choose the operation (e. g., read, program, or erase) to be performed on the flash memory (this is called the first cycle), and then input the information necessary for execution of the com- mand (e.g, address and data) and control signals (this is called the second cycle). when this is done, the M38B79ff executes the specified operation. table 15 shows the software commands and the input/output in- formation in the first and the second cycles. the input address is ___ latched internally at the falling edge of the we input; software commands and other input data are latched internally at the rising ___ edge of the we input. the following explains each software command. refer to figures 87 to 89 for details about the signal input/output timings. table 15 software command (parallel input/output mode) symbol read program program verify erase erase verify reset device identification address input verify address first cycle data input 00 16 40 16 c0 16 20 16 a0 16 ff 16 90 16 address input read address program address adi second cycle data i/o read data (output) program data (input) verify data (output) 20 16 (input) verify data (output) ff 16 (input) ddi (output) note: adi = device identification address : manufacturer s code 00000 16 , device code 00001 16 ddi = device identification data : manufacturer s code 1c 16 , device code d0 16 can be v il or v ih . address valid address t rc t a(ce) t wrr t df t a(oe) t dh t olz floating floating t clz t a(ad) v ih v il v ih v il v ih v il v ih v il v oh v ol ce oe we data dout
81 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. read command the microcomputer enters the read mode by inputting command code 00 16 in the first cycle. the command code is latched into ___ the internal command latch at the rising edge of the we input. when the address of a memory location to be read is input in the second cycle, with control signals input at the timing shown in figure 87, the M38B79ff outputs the contents of the specified ad- dress from the data i/o pins to the external. the read mode is retained until any other command is latched into the command latch. consequently, once the M38B79ff enters the read mode, the user can read out the successive memory contents simply by changing the input address and executing the second cycle only. any command other than the read command must be in- put beginning from its command code over again each time the user execute it. the contents of the command latch immediately after power-on is 00 16 . fig. 87 timings during reading address valid address t wc t ch t cs t rc t a(ce) t df t wrr t wp t rrw t a(oe) t dh t dh t vsc t clz t olz t ds t a(ad) v ih v il v ih v il v ih v il v ih v il v ih v il v pp h v pp l ce oe we data v pp dout 00 16
82 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. program command the microcomputer enters the program mode by inputting com- mand code 40 16 in the first cycle. the command code is latched ___ into the internal command latch at the rising edge of the we input. when the address which indicates a program location and data is input in the second cycle, the M38B79ff internally latches the ad- ___ dress at the falling edge of the we input and the data at the rising ___ edge of the we input. the M38B79ff starts programming at the ___ rising edge of the we input in the second cycle and finishes pro- gramming within 10 s as measured by its internal timer. programming is performed in units of bytes. note: a programming operation is not completed by executing the program command once. always be sure to execute a pro- gram verify command after executing the program command. when the failure is found in this verification, the user must re- peatedly execute the program command until the pass. refer to figure 90 for the programming flowchart. program verify command the microcomputer enters the program verify mode by inputting command code c0 16 in the first cycle. this command is used to verify the programmed data after executing the program com- mand. the command code is latched into the internal command ___ latch at the rising edge of the we input. when control signals are input in the second cycle at the timing shown in figure 88, the M38B79ff outputs the programmed address s contents to the ex- ternal. since the address is internally latched when the program command is executed, there is no need to input it in the second cycle. fig. 88 input/output timings during programming (verify data is output at the same timing as for read.) address program program verify program address t wc t cs t rrw t wp t wph t wp t dp t ds 40 16 d in c0 16 dout t ds t dh t dh verify data output t dh t vsc t ds t wp t wrr t cs t cs t ch t ch t ch t as t ah v ih v il v ih v il v ih v il v ih v il v ih v il v pp h v pp l ce oe we data v pp
83 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. erase command the erase command is executed by inputting command code 20 16 in the first cycle and command code 20 16 again in the second cycle. the command code is latched into the internal command ___ latch at the rising edges of the we input in the first cycle and in the second cycle, respectively. the erase operation is initiated at ___ the rising edge of the we input in the second cycle, and the memory contents are collectively erased within 9.5 ms as mea- sured by the internal timer. note that data 00 16 must be written to all memory locations before executing the erase command. note: an erase operation is not completed by executing the erase command once. always be sure to execute an erase verify command after executing the erase command. when the fail- ure is found in this verification, the user must repeatedly ex- ecute the erase command until the pass. refer to figure 90 for the erase flowchart. fig. 89 input/output timings during erasing (verify data is output at the same timing as for read.) erase verify command the user must verify the contents of all addresses after complet- ing the erase command. the microcomputer enters the erase verify mode by inputting the verify address and command code a0 16 in the first cycle. the address is internally latched at the fall- ___ ing edge of the we input, and the command code is internally ___ latched at the rising edge of the we input. when control signals are input in the second cycle at the timing shown in figure 89, the M38B79ff outputs the contents of the specified address to the external. note: if any memory location where the contents have not been erased is found in the erase verify operation, execute the op- eration of erase erase verify over again. in this case, however, the user does not need to write data 00 16 to memory locations before erasing. address erase erase verify verify address t wc t cs t rrw t wp t wph t wp t de t ds 20 16 20 16 a0 16 dout t ds t dh t dh verify data output t dh t vsc t ds t wp t wrr t cs t cs t ch t ch t ch t as t ah v ih v il v ih v il v ih v il v ih v il v ih v il v pp h v pp l ce oe we data v pp
84 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. reset command the reset command provides a means of stopping execution of the erase or program command safely. if the user inputs command code ff 16 in the second cycle after inputting the erase or program command in the first cycle and again input command code ff 16 in the third cycle, the erase or program command is disabled (i.e., reset), and the M38B79ff is placed in the read mode. if the reset command is executed, the contents of the memory does not change. device identification code command by inputting command code 90 16 in the first cycle, the user can read out the device identification code. the command code is latched into the internal command latch at the rising edge of the ___ we input. at this time, the user can read out manufacture s code 1c 16 (i.e., mitsubishi) by inputting 0000 16 to the address input pins in the second cycle; the user can read out device code d0 16 (i. e., 1m-bit flash memory) by inputting 0001 16 . these command and data codes are input/output at the same tim- ing as for read.
85 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 90 programming/erasing algorithm flow chart start v cc = 5 v, v pp = v pp h adrs = first location x = 0 write program command write program data duration = 10 s x = x + 1 write program-verify command 40 16 d in c0 16 00 16 duration = 6 s x = 25 ? last adrs ? no inc adrs write read command v pp = v pp l device passed device failed verify byte ? verify byte ? fail fail program erase yes yes no pass pass start v cc = 5 v, v pp = v pp h adrs = first location x = 0 write erase command program all bytes = 00 16 all bytes = 00 16 ? write erase command duration = 9.5 ms x = x + 1 write erase-verify command 20 16 20 16 a0 16 00 16 duration = 6 s x = 1000 ? last adrs ? no inc adrs write read command v pp = v pp l device passed device failed verify byte ? verify byte ? fail fail yes yes no pass pass yes no
86 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. table 16 dc electrical characteristics (t a = 25 ?, v cc = 5 v ?10 %, unless otherwise noted) symbol max. 1 100 15 15 15 10 100 100 30 30 0.2vcc v cc v cc + 1.0 12.6 __ v cc = 5.5 v, ce = v ih v cc = 5.5 v, __ ce = v cc 0.2 v __ v cc = 5.5 v, ce = v il , t rc = 150 ns, i out = 0 ma v pp = v pp h v pp = v pp h 0 v pp v cc v cc 87 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (2) flash memory mode 2 (serial i/o mode) the M38B79ff has a function to serially input/output the software commands, addresses, and data required for operation on the in- ternal flash memory (e. g., read, program, and erase) using only a few pins. this is called the serial i/o (input/output) mode. this mode can be selected by driving the sda (serial data input/out- __ put), sclk (serial clock input ), and oe pins high after connecting wires as shown in figures 91 and powering on the v cc pin and then applying v pp h to the v pp pin. in the serial i/o mode, the user can use six types of software com- mands: read, program, program verify, erase, erase verify and error check. serial input/output is accomplished synchronously with the clock, beginning from the lsb (lsb first). fig. 91 pin connection of M38B79ff when operating in serial i/o mode m 3 8 b 7 9 f f f p * p 4 7 / f l d 3 9 * p 0 0 / f l d 8 * p 0 3 / f l d 1 1 * p 0 4 / f l d 1 2 * p 0 5 / f l d 1 3 * p 0 6 / f l d 1 4 * p 0 7 / f l d 1 5 * p 1 1 / f l d 1 7 * p 1 2 / f l d 1 8 * p 1 3 / f l d 1 9 * p 1 4 / f l d 2 0 * p 1 5 / f l d 2 1 * p 1 6 / f l d 2 2 * p 1 7 / f l d 2 3 * p 1 0 / f l d 1 6 * p 0 1 / f l d 9 * p 0 2 / f l d 1 0 v e e * p 4 6 / f l d 3 8 * p 4 3 / f l d 3 5 * p 4 2 / f l d 3 4 * p 4 1 / f l d 3 3 * p 4 0 / f l d 3 2 * p 3 7 / f l d 3 1 * p 3 6 / f l d 3 0 * p 3 5 / f l d 2 9 * p 3 4 / f l d 2 8 * p 3 3 / f l d 2 7 * p 3 2 / f l d 2 6 * p 3 1 / f l d 2 5 * p 3 0 / f l d 2 4 * p 4 5 / f l d 3 7 * p 4 4 / f l d 3 6 p b 5 / s o u t 1 p b 4 / s c l k 1 1 p b 3 / s s t b 1 p a 6 / a n 6 p a 7 / a n 7 v r e f a v s s p 9 0 / s i n 3 / a n 8 p 9 1 / s o u t 3 / a n 9 p 9 2 / s c l k 3 / a n 1 0 p 9 4 / r t p 1 / a n 1 2 p 9 5 / r t p 0 / a n 1 3 p 9 6 / p w m 0 / a n 1 4 p 9 7 / b u z 0 2 / a n 1 5 p b 2 / s b u s y 1 p a 1 / a n 1 p a 0 / a n 0 p 8 1 / x c o u t p 8 0 / x c i n p 7 4 / p w m 1 p 7 3 / i n t 3 / d i m o u t p 7 2 / i n t 2 p 7 1 / i n t 1 p 7 0 / i n t 0 p a 5 / a n 5 p b 0 / s c l k 1 2 / s v i n / d a p b 1 / s r d y 1 p 7 5 / t 1 o u t x i n x o u t v c c p 7 6 / t 3 o u t v s s p 7 7 / i n t 4 / b u z 0 1 r e s e t p a 4 / a n 4 p a 3 / a n 3 p a 2 / a n 2 * p 2 0 / f l d 0 * p 2 1 / f l d 1 * p 2 2 / f l d 2 * p 2 3 / f l d 3 * p 2 4 / f l d 4 * p 2 5 / f l d 5 * p 2 6 / f l d 6 * p 2 7 / f l d 7 p b 6 / s i n 1 * p 5 1 / f l d 4 1 * p 5 0 / f l d 4 0 * p 5 3 / f l d 4 3 * p 5 2 / f l d 4 2 * p 5 5 / f l d 4 5 * p 5 4 / f l d 4 4 * p 5 7 / f l d 4 7 * p 5 6 / f l d 4 6 * p 6 1 / f l d 4 9 * p 6 0 / f l d 4 8 * p 6 3 / f l d 5 1 * p 6 2 / f l d 5 0 p 6 5 / t x d / f l d 5 3 p 6 4 / r x d / f l d 5 2 p 6 7 / s r d y 2 / s c l k 2 2 / f l d 5 5 p 6 6 / s c l k 2 1 / f l d 5 4 p 8 2 / c n t r 1 c n v s s p 8 3 / c n t r 0 / c n t r 2 p 9 3 / s r d y 3 / a n 1 1 o e v p p v c c s d a s c l k b u s y v s s ? : c o n n e c t t o t h e c e r a m i c o s c i l l a t i o n c i r c u i t . : h i g h - b r e a k d o w n - v o l t a g e o u t p u t p o r t : t o t a l i n g 5 2 i n d i c a t e s t h e f l a s h m e m o r y p i n . 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 0 0 * ? p a c k a g e t y p e : 1 0 0 p 6 s - a
88 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. table 19 pin description (flash memory serial i/o mode) v cc , v ss cnv ss _____ reset x in x out av ss v ref p0 0 p0 7 p1 0 p1 7 p2 0 p2 7 p3 0 p3 6 p3 7 p4 0 p4 7 p5 0 p5 7 p6 0 p6 3 , p6 5 p6 4 p6 6 p6 7 p7 0 p7 7 p8 0 p8 3 p9 0 p9 7 pa 0 pa 7 pb 0 pb 6 v ee pin power supply v pp input reset input clock input clock output analog supply input reference voltage input input port p0 input port p1 input port p2 input port p3 control signal input input port p4 input port p5 input port p6 sda i/o sclk input busy output input port p7 input port p8 input port p9 input port pa input port pb pull-down power supply name input input input output input input input input input input input input input i/o input output input input input input input input /output functions supply 5 v 10 % to v cc and 0 v to v ss . connect to 11.7 v to 12.6 v. connect to v ss . connect a ceramic resonator between x in and x out . connect to v ss . input an arbitrary level between the range of v ss and v cc . input h or l , or keep them open. input h or l , or keep them open. input h or l , or keep them open. input h or l , or keep them open. __ oe input pin input h or l , or keep them open. input h or l , or keep them open. input h or l to p6 0 p6 3 , p6 5 , or keep them open. this pin is for serial data i/o. this pin is for serial clock input. this pin is for busy signal output. input h or l , or keep them open. input h or l , or keep them open. input h or l , or keep them open. input h or l , or keep them open. input h or l , or keep them open. keep this open.
89 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. functional outline (serial i/o mode) in the serial i/o mode, data is transferred synchronously with the clock using serial input/output. the input data is read from the sda pin into the internal circuit synchronously with the rising edge of the serial clock pulse; the output data is output from the sda pin synchronously with the falling edge of the serial clock pulse. data is transferred in units of eight bits. in the first transfer, the user inputs the command code. this is fol- lowed by address input and data input/output according to the contents of the command. table 20 shows the software com- mands used in the serial i/o mode. the following explains each software command. table 20 software command (serial i/o mode) read program program verify erase erase verify error check number of transfers command first command code input 00 16 40 16 c0 16 20 16 a0 16 80 16 read address l (input) program address l (input) verify data (output) 20 16 (input) verify address l (input) error code (output) second read address h (input) program address h (input) verify address h (input) third fourth read data (output) program data (input) verify data (output) input command code 00 16 in the first transfer. proceed and input the low-order 8 bits and the high-order 8 bits of the address and __ pull the oe pin low. when this is done, the M38B79ff reads out the contents of the specified address, and then latchs it into the in- __ ternal data latch. when the oe pin is released back high and se- rial clock is input to the sclk pin, the read data that has been latched into the data latch is serially output from the sda pin. fig. 92 timings during reading l sclk busy oe sda t ch a 0 a 7 a 8 a 15 d 0 d 7 t ch t cr command code input (00 16 ) read address input (l) read address input (h) read data output t wr read t rc note : when outputting the read data, the sda pin is switched for output at the first falling edge of sclk. the sda pin is placed in the floating state during the period of th (c-e) after the last rising edge of sclk (at the 8th bit). 00000000
90 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. input command code 40 16 in the first transfer. proceed and input the low-order 8 bits and the high-order 8 bits of the address and then program data. programming is initiated at the last rising edge of the serial clock during program data transfer. the busy pin is driven high during program operation. programming is completed within 10 s as measured by the internal timer, and the busy pin is pulled low. note : a programming operation is not completed by executing the program command once. always be sure to execute a pro- gram verify command after executing the program command. when the failure is found in the verification, the user must re- peatedly execute the program command until the pass in the verification. refer to figure 90 for the programming flowchart. input command code c0 16 in the first transfer. proceed and drive __ the oe pin low. when this is done, the M38B79ff verify-reads the programmed address s contents, and then latchs it into the in- __ ternal data latch. when the oe pin is released back high and se- rial clock is input to the sclk pin, the verify data that has been latched into the data latch is serially output from the sda pin. fig. 94 timings during program verify fig. 93 timings during programming sclk busy oe sda t ch a 0 00000010 a 7 a 8 a 15 d 0 d 7 t ch t ch t pc command code input (40 16 ) program address input (l) program address input (h) program data input t wp program sclk busy oe sda d 0 d 7 t crpv command code input (c0 16 ) verify data output t wr verify read t rc note: when outputting the verify data, the sda pin is switched for output at the first falling edge of sclk. the sda pin is placed in the floating state during the period of th (c-e) after the last rising edge of sclk (at the 8th bit). 00000011 l
91 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. input command code 20 16 in the first transfer and command code 20 16 again in the second transfer. when this is done, the M38B79ff executes an erase command. erase is initiated at the last rising edge of the serial clock. the busy pin is driven high during the erase operation. erase is completed within 9.5 ms as measured by the internal timer, and the busy pin is pulled low. note that data 00 16 must be written to all memory locations before executing the erase command. note: a erase operation is not completed by executing the erase command once. always be sure to execute a erase verify command after executing the erase command. when the fail- ure is found in the verification, the user must repeatedly ex- ecute the erase command until the pass in the verification. refer to figure 90 for the erase flowchart. fig. 95 timings at erasing the user must verify the contents of all addresses after complet- ing the erase command. input command code a0 16 in the first transfer. proceed and input the low-order 8 bits and the high-order __ 8 bits of the address and pull the oe pin low. when this is done, the M38B79ff reads out the contents of the specified address, __ and then latchs it into the internal data latch. when the oe pin is released back high and serial clock is input to the sclk pin, the verify data that has been latched into the data latch is serially out- put from the sda pin. note: if any memory location where the contents have not been erased is found in the erase verify operation, execute the op- eration of erase erase verify over again. in this case, however, the user does not need to write data 00 16 to memory locations before erasing. fig. 96 timings during erase verify tw e sclk busy oe sda t ch t ec 00000100 00000100 command code input (20 16 ) command code input (20 16 ) erase h l sclk busy oe sda t ch a 0 a 7 a 8 a 15 d 0 d 7 t ch t crev command code input (a0 16 ) verify address input (l) verify address input (h) verify data output t wr verify read t rc note : when outputting the verify data, the sda pin is switched for output at the first falling edge of sclk. the sda pin is placed in the floating state during the period of th (c-e) after the last rising edge of sclk (at the 8th bit). 00000101
92 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. input command code 80 16 in the first transfer, and the M38B79ff outputs error information from the sda pin, beginning at the next falling edge of the serial clock. if the lsb bit of the 8-bit error infor- mation is 1, it indicates that a command error has occurred. a command error means that some invalid commands other than commands shown in table 20 has been input. when a command error occurs, the serial communication circuit sets the corresponding flag and stops functioning to avoid an erro- neous programming or erase. when being placed in this state, the serial communication circuit does not accept the subsequent serial clock and data (even including an error check command). there- fore, if the user wants to execute an error check command, temporarily drop the v pp pin input to the v pp l level to terminate the serial input/output mode. then, place the M38B79ff into the serial i/o mode back again. the serial communication circuit is re- set by this operation and is ready to accept commands. the error flag alone is not cleared by this operation, so the user can exam- ine the serial communication circuit s error conditions before reset. this examination is done by the first execution of an error check command after the reset. the error flag is cleared when the user has executed the error check command. because the error flag is undefined immediately after power-on, always be sure to execute the error check command. fig. 97 timings at error checking sclk busy oe sda e0 t ch command code input (80 16 ) error flag output 00000001 ?????? note: when outputting the error flag, the sda pin is switched for output at the first falling edge of the serial clock. the sda pin i s placed in the floating state during the period of th (c-e) after the last rising edge of the serial clock (at the 8th bit). ? h l
93 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. ns ns ns ns s s ns s ms ns ns ns ns ns ns ns ns ns ns ns dc electrical characteristics (ta = 25 c, v cc = 5 v ?10 %, v pp = 11.7 to 12.6 v, unless otherwise noted) i cc , i pp -relevant standards during read, program, and erase are the same as in the parallel input/output mode. v ih , v il , v oh , v ol , i ih , and __ i il for the sclk, sda, busy, oe pins conform to the microcomputer modes. table 21 ac electrical characteristics (t a = 25 c, v cc = 5 v ?10 %, v pp = 11.7 to 12.6 v, f(x in ) = 4 mhz, unless otherwise noted) symbol max. 10 9.5 90 312.5 (note 4) t ch t cr t wr t rc t crpv t wp t pc t crev t we t ec t c(ck) t w(ckh) t w(ckl) t r(ck) t f(ck) t d(c-q) t h(c-q) t h(c-e) t su(d-c) t h(c-d) serial transmission interval read waiting time after transmission read pulse width transfer waiting time after read waiting time before program verify programming time transfer waiting time after programming waiting time before erase verify erase time transfer waiting time after erase sclk input cycle time sclk high-level pulse width sclk low-level pulse width sclk rise time sclk fall time sda output delay time sda output hold time sda output hold time (only the 8th bit) sda input set up time sda input hold time parameter unit min. 625 (note 1) 625 (note 1) 500 (note 2) 625 (note 1) 6 625 (note 1) 6 625 (note 1) 250 100 100 20 20 0 0 187.5 (note 3) 30 90 limits notes 1: when f(x in ) = 4 mhz or less, calculate the minimum value according to formula 1. formula 1 : 10 6 2: when f(x in ) = 4 mhz or less, calculate the minimum value according to formula 2. formula 2 : 10 6 3: when f(x in ) = 4 mhz or less, calculate the minimum value according to formula 3. formula 3 : 10 6 4: when f(x in ) = 4 mhz or less, calculate the minimum value according to formula 4 formula 4 : 10 6 2500 f(x in ) 2000 f(x in ) 1250 f(x in ) 750 f(x in ) ac waveforms sclk sda input test conditions for ac characteristics output timing voltage : v ol = 0.8 v, v oh = 2.0 v input timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc sda output t c(ck) t r(ck) t d(c-q) t su(d-c) t h(c-d) t h(c-e) t h(c-q) t f(ck) t w(ckl) t w(ckh)
94 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (3) flash memory mode 3 (cpu reprogramming mode) the M38B79ff has the cpu reprogramming mode where a built- in flash memory is handled by the central processing unit (cpu). in cpu reprogramming mode, the flash memory is handled by writing and reading to/from the flash memory control register (see figure 98) and the flash command register (see figure 99). the cnv ss pin is used as the v pp power supply pin in cpu repro- gramming mode. it is necessary to apply the power-supply voltage of v pp h from the external to this pin. functional outline (cpu reprogramming mode) figure 98 shows the flash memory control register bit configura- tion. figure 99 shows the flash command register bit configuration. bit 0 of the flash memory control register is the cpu reprogram- ming mode select bit. when this bit is set to 1 and v pp h is applied to the cnvss/v pp pin, the cpu reprogramming mode is selected. whether the cpu reprogramming mode is realized or not is judged by reading the cpu reprogramming mode monitor flag (bit 2 of the flash memory control register). bit 1 is a busy flag which becomes 1 during erase and program execution. whether these operations have been completed or not is judged by checking this flag after each command of erase and the pro- gram is executed. bits 4, 5 of the flash memory control register are the erase/pro- gram area select bits. these bits specify an area where erase and program is operated. when the erase command is executed after an area is specified by these bits, only the specified area is erased. only for the specified area, programming is enabled; for the other areas, programming is disabled. figure 100 shows the cpu mode register bit configuration in the cpu reprogramming mode. fig. 98 flash memory control register bit configuration 76543210 0 0 flash memory control regsiter (fcon : address 0efe 16 ) cpu reprogramming mode select bit (note) 0 : cpu reprogramming mode is invalid. (normal operation mode) 1 : when applying 0 v or v pp l to cnv ss /v pp pin, cpu reprogramming mode is invalid. when applying v pp h to cnv ss /v pp pin, cpu reprogramming mode is valid. erase/program busy flag 0 : erase and program are completed or not have been executed. 1 : erase/program is being executed. cpu reprogramming mode monitor flag 0 : cpu reprogramming mode is invalid. 1 : cpu reprogramming mode is valid. erase/program area select bits 0 0 : addresses 1000 16 to ffff 16 (total 60 kbytes) 0 1 : addresses 1000 16 to 7fff 16 (total 28 kbytes) 1 0 : addresses 8000 16 to ffff 16 (total 32 kbytes) 1 1 : not available fix this bit to 0 . fix this bit to 0 . note: bit 0 can be reprogrammed only when 0 v is applied to the cnv ss /v pp pin. not used (returns 0 when read)
95 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. the operation procedure in cpu reprogramming mode is de- scribed below. < beginning procedure > ? apply 0 v to the cnvss/v pp pin for reset release. ? set the cpu mode register. (see figure 100) ? after cpu reprogramming mode control program is transferred to internal ram, jump to this control program on ram. (the follow- ing operations are controlled by this control program). ? set 1 to the cpu reprogramming mode select bit. ? apply v pp h to the cnv ss /v pp pin. ? wait till cnv ss /v pp pin becomes 12 v. ? read the cpu reprogramming mode monitor flag to confirm whether the cpu reprogramming mode is valid. ? the operation of the flash memory is executed by software-com- mand-writing to the flash command register . note: the following are necessary other than this: control for data which is input from the external (serial i/o etc.) and to be programmed to the flash memory initial setting for ports etc. writing to the watchdog timer < release procedure > ? apply 0v to the cnv ss /v pp pin. ? wait till cnv ss /v pp pin becomes 0v. ? set the cpu reprogramming mode select bit to 0 . each software command is explained as follows. when 00 16 is written to the flash command register, the M38B79ff enters the read mode. the contents of the corre- sponding address can be read by reading the flash memory (for instance, with the lda instruction etc.) under this condition. the read mode is maintained until another command code is written to the flash command register. accordingly, after setting the read mode once, the contents of the flash memory can continuously be read. after reset and after the reset command is executed, the read mode is set. fig. 99 flash command register bit configuration fig. 100 cpu mode register bit configuration in cpu rewriting mode writing of software command 00 16 40 16 c0 16 20 16 + 20 16 a0 16 ff 16 + ff 16 read command program command program verify command erase command erase verify command reset command note: the flash command register is write-only register. flash command register (fcmd : address 0eff 16 ) 76 5 4 3 2 1 0 c p u m o d e r e g i s t e r ( c p u m : a d d r e s s 0 0 3 b 1 6 ) b 7 b 0 s t a c k p a g e s e l e c t i o n b i t 0 : 0 p a g e 1 : 1 p a g e r e s e r v e d ( d o n o t w r i t e 0 t o t h i s b i t w h e n u s i n g x c i n x c o u t o s c i l l a t i o n f u n c t i o n . ) p r o c e s s o r m o d e b i t s b 1 b 0 0 0 : s i n g l e - c h i p m o d e 0 1 : n o t a v a i l a b l e 1 x : n o t a v a i l a b l e p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n ( s t o p o s c i l l a t i n g ) 1 : x c i n x c o u t o s c i l l a t i n g f u n c t i o n m a i n c l o c k ( x i n x o u t ) s t o p b i t 0 : o s c i l l a t i n g 1 : s t o p p e d m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b 7 b 6 0 0 : = f ( x i n ) ( h i g h - s p e e d m o d e ) 0 1 : = f ( x i n ) / 4 ( m i d d l e - s p e e d m o d e ) 1 0 : = f ( x c i n ) / 2 ( l o w - s p e e d m o d e ) 1 1 : n o t a v a i l a b l e 00
96 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. when 40 16 is written to the flash command register, the M38B79ff enters the program mode. subsequently to this, if the instruction (for instance, sta instruction) for writing byte data in the address to be programmed is executed, the control circuit of the flash memory executes the program. the erase/program busy flag of the flash memory control register is set to 1 when the program starts, and becomes 0 when the program is completed. accordingly, after the write in- struction is executed, cpu can recognize the completion of the program by polling this bit. the programmed area must be specified beforehand by the erase/ program area select bits. during programming, watchdog timer stops with ffff 16 set. note: a programming operation is not completed by executing the program command once. always be sure to execute a pro- gram verify command after executing the program command. when the failure is found in this verification, the user must re- peatedly execute the program command until the pass. refer to figure 101 for the flow chart of the programming. when c0 16 is written to the flash command register, the M38B79ff enters the program verify mode. subsequently to this, if the instruction (for instance, lda instruction) for reading byte data from the address to be verified (i.e., previously programmed address), the contents which has been written to the address ac- tually is read. cpu compares this read data with data which has been written by the previous program command. in consequence of the compari- son, if not agreeing, the operation of program program verify must be executed again. when writing 20 16 twice continuously to the flash command reg- ister, the flash memory control circuit performs erase to the area specified beforehand by the erase/program area select bits. erase/program busy flag of the flash memory control register be- comes 1 when erase begins, and it becomes 0 when erase completes. accordingly, cpu can recognize the completion of erase by polling this bit. data 00 16 must be written to all areas to be erased by the pro- gram and the program verify commands before the erase command is executed. during erasing, watchdog timer stops with ffff 16 set. note: the erasing operation is not completed by executing the erase command once. always be sure to execute an erase verify command after executing the erase command. when the fail- ure is found in this verification, the user must repeatedly ex- ecute the erase command until the pass. refer to figure 101 for the erasing flowchart. when a0 16 is written to the flash command register, the M38B79ff enters the erase verify mode. subsequently to this, if the instruction (for instance, lda instruction) for reading byte data from the address to be verified, the contents of the address is read. cpu must erase and verify to all erased areas in a unit of ad- dress. if the address of which data is not ff 16 (i.e., data is not erased) is found, it is necessary to discontinue erasure verification there, and execute the operation of erase erase verify again. note: by executing the operation of erase erase verify again when the memory not erased is found. it is unnecessary to write data 00 16 before erasing in this case. the reset command is a command to discontinue the program or erase command on the way. when ff 16 is written to the command register two times continuously after 40 16 or 20 16 is written to the flash command register, the program, or erase command becomes invalid (reset), and the M38B79ff enters the reset mode. the contents of the memory does not change even if the reset com- mand is executed. dc electric characteristics note: the characteristic concerning the flash memory part are the same as the characteristic of the parallel i/o mode. ac electric characteristics note: the characteristics are the same as the characteristic of the microcomputer mode.
97 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 101 flowchart of program/erase operation at cpu reprogramming mode erase program busy flag = 0 start adrs = first location x = 0 write program command write program data wait 1 s x = x + 1 write program-verify command 40 16 din c0 16 00 16 duration = 6 s x = 25 ? last adrs ? no inc adrs write read command device passed device failed verify byte ? verify byte ? fail fail program erase yes yes no pass pass start adrs = first location x = 0 write erase command program all bytes = 00 16 all bytes = 00 16 ? write erase command x = x + 1 write erase-verify command 20 16 20 16 a0 16 00 16 duration = 6 s x = 1000 ? last adrs ? no inc adrs write read command device passed device failed verify byte ? verify byte ? fail fail yes yes no pass pass yes no erase program busy flag = 0 wait 1 s no yes yes no
98 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before perform- ing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to 1 , then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: the data transfer instruction (lda, etc.) the operation instruction when the index x mode flag (t) is 1 the instruction with the addressing mode which uses the value of a direction register as an index the bit-test instruction (bbc or bbs, etc.) to a direction register the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o using an external clock when using an external clock, input h to the external clock input pin and clear the serial i/o interrupt request bit before executing serial i/o transfer and serial i/o automatic transfer. using an internal clock when using an internal clock, set the synchronous clock to the in- ternal clock, then clear the serial i/o interrupt request bit before executing serial i/o transfer and serial i/o automatic transfer. automatic transfer serial i/o when using the automatic transfer serial i/o mode of the serial i/ o1, set an automatic transfer interval as the following. otherwise the serial data might be incorrectly transmitted/re- ceived. set an automatic transfer interval for each 1-byte data transfer as the following: (1) not using fld controller keep the interval for 5 cycles or more of internal system clock from clock rising of the last bit of 1-byte data. (2) using fld controller (a) not using gradation display keep the interval for 17 cycles or more of internal system clock from clock rising of the last bit of 1-byte data. (b) using gradation display keep the interval for 27 cycles or more of internal system clock from clock rising of the last bit of 1-byte data. a-d converter the comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 250 khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conver- sion. d-a converter the accuracy of the d-a converter becomes rapidly poor under the v cc = 4.0 v or less condition; a supply voltage of v cc 4.0 v is recommended. when a d-a converter is not used, set the value of d-a conversion register to 00 16 . instruction execution time the instruction execution time is obtained by multiplying the pe- riod of the internal clock by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the period of the internal clock is half of the x in period in high- speed mode.
99 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. notes on usage handling of power source pins in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (v cc pin) and gnd pin (v ss pin), between power source pin (v cc pin) and analog power source input pin (av ss pin), and between program power source pin (cnvss/v pp ) and gnd pin for flash memory version when on-board reprogramming is executed. besides, connect the capacitor to as close as pos- sible. for bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 f 0.1 f is recommended. flash memory version the cnv ss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, connect a track between cnv ss pin and v ss pin or v cc pin with 1 to 10 k ? resistance. the mask rom version track of cnv ss pin has no operational in- terference even if it is connected to vss pin or vcc pin via a resistor. data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom confirmation form 2.mark specification form 3.data to be written to rom, in eprom form (three identical cop- ies) or in one floppy disk.
100 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. electrical characteristics table 22 absolute maximum ratings power source voltages pull-down power source voltages input voltage p6 4 p6 7 , p7 0 p7 7 , p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 input voltage p1 0 p1 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 3 input voltage reset, x in , cnv ss input voltage x cin output voltage p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 3 output voltage p6 4 p6 7 , p8 0 p8 3 , p7 0 p7 7 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 , x out , x cout power dissipation operating temperature storage temperature v cc v ee v i v i v i v i v o v o p d t opr t stg symbol parameter conditions ratings 0.3 to 6.5 v cc 48 to v cc +0.3 0.3 to v cc +0.3 v cc 48 to v cc +0.3 0.3 to v cc +0.3 0.3 to v cc +0.3 v cc 48 to v cc +0.3 0.3 to v cc +0.3 800 800 12.5 ? (ta 65) 20 to 85 40 to 125 v v v v v v v v mw mw c c unit t a = 20 to 65 c t a = 65 to 85 c all voltages are based on v ss . output transistors are cut off. 5.5 5.5 5.5 v cc v cc v cc v cc v cc v cc v cc v cc v cc 0.25v cc 0.16v cc 0.2v cc 0.2v cc 0.2v cc high-speed mode middle/low-speed mode power source voltage (flash memory version) power source voltage pull-down power source voltage analog reference voltage analog power source voltage analog input voltage an 0 an 15 h input voltage p7 0 p7 7 , p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 h input voltage p6 4 p6 7 h input voltage p1 0 p1 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 3 h input voltage rxd, s clk21 , s clk22 h input voltage x in , x cin , reset, cnvss l input voltage p7 0 p7 7 , p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 l input voltage p6 4 p6 7 l input voltage p1 0 p1 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 3 l input voltage rxd, s clk21 , s clk22 l input voltage x in , x cin , reset, cnvss v cc v cc v ss v ee v ref av ss v ia v ih v ih v ih v ih v ih v il v il v il v il v il symbol parameter limits min. v v v v v v v v v v v v v v v v v v v unit table 23 recommended operating conditions (v cc = 4.0 to 5.5 v, t a = 20 to 85 c, unless otherwise noted) 4.0 2.7 4.0 vcc 43 2.0 3.0 0 0.75v cc 0.4v cc 0.52v cc 0.8v cc 0.8v cc 0 0 0 0 0 5.0 5.0 5.0 0 0 typ. max. when a-d converter is used when d-a converter is used power source voltage (mask rom version)
101 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. table 24 recommended operating conditions (v cc = 4.0 to 5.5 v, t a = 20 to 85 c, unless otherwise noted) 240 60 100 60 120 30 50 40 10 10 18 5 5 250 4.2 50 h total peak output current (note 1) p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 0 p7 7 h total peak output current (note 1) p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 l total peak output current (note 1) p6 4 p6 7 , p7 0 p7 7 l total peak output current (note 1) p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 h total average output current (note 1) p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 3 h total average output current (note 1) p6 4 p6 7 , p7 0 p7 7 , p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 l total average output current (note 1) p6 4 p6 7 , p7 0 p7 7 , p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 h peak output current (note 2) p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 3 h peak output current (note 2) p6 4 p6 7 , p7 0 p7 7 , p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 l peak output current (note 2) p6 4 p6 7 , p7 0 p7 7 , p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 h average output current (note 3) p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 3 h average output current (note 3) p6 4 p6 7 , p7 0 p7 7 , p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 l average output current (note 3) p6 4 p6 7 , p7 0 p7 7 , p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 clock input frequency for timers 2, 4, and x (duty cycle 50 %) main clock input oscillation frequency (note 4) sub-clock input oscillation frequency (notes 4, 5) i oh(peak) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i oh(peak) i oh(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) f(cntr) f(x in ) f(x cin ) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma ma ma ma khz mhz khz unit typ. max. notes 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an aver- age value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current i ol (avg), i oh (avg) are average value measured over 100 ms. 4: when the oscillation frequency has a duty cycle of 50%. 5: when using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. 32.768
102 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. table 25 electrical characteristics (v cc = 4.0 to 5.5 v, t a = 20 to 85 c, unless otherwise noted) min. typ. max. symbol parameter limits unit h output voltage p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 -p5 7 , p6 0 p6 3 h output voltage p6 4 p6 7 , p7 0 p7 7 , p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 l output voltage p6 4 p6 7 , p7 0 p7 7 , p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 hysteresis rxd, s clk21 , s clk22 , s rdy1 , p7 0 p7 3 , p7 7 , p8 2 p8 3 , p9 0 p9 2 , pb 0 , pb 2 , pb 4 pb 6 hysteresis reset, x in hysteresis x cin h input current p6 4 p6 7 , p7 0 p7 7 , p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 h input current p1 0 p1 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 -p5 7 , p6 0 p6 3 (note) h input current reset, cnvss, x cin h input current x in l input current p6 4 p6 7 , p7 0 p7 7 , p8 0 p8 3 , p9 0 p9 7 , pa 0 pa 7 , pb 0 pb 6 l input current p1 0 p1 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 3 (note) l input current reset, cnvss, x cin l input current x in v oh v oh v ol v t+ v t v t+ v t v t+ v t i ih i ih i ih i ih i il i il i il i il i oh = 18 ma i oh = 10 ma i ol = 10 ma v i = v cc v i = v cc v i = v cc v i = v cc v i = v ss pull-up off v cc = 5 v , v i = v ss pull-up on v cc = 3 v , v i = v ss pull-up on v i = v ss v i = v ss v i = v ss test conditions v cc 2.0 v cc 2.0 30 6.0 2.0 5.0 5.0 5.0 5.0 140 45 5.0 5.0 0.4 0.5 0.5 4.0 70 25 4.0 note: except when reading ports p1, p3, p4, p5 or p6. v v v v v v a a a a a a a a a a
103 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. table 26 electrical characteristics (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted) power source current limits parameter min. typ. max. symbol unit test conditions 900 10 5.5 15 55 20 1 10 i cc ta = 25 c ta = 85 c 600 1 7.0 1 3 1 20 8 0.6 0.1 a a a v ma ma ma ma a a ma a a i load i leak i readh v ram output load current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 , (p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 3 at option) output leak current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 3 h read current p1 0 p1 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 3 ram hold voltage v ee = v cc 43 v , v ol =v cc output transistors off v ee = v cc 43 v , v ol =v cc 43 v output transistors off v i = 5 v when clock is stopped high-speed mode, vcc = 5 v, f(x in ) = 4.2 mhz f(x cin ) = 32.768 khz output transistors off high-speed mode, vcc = 5 v, f(x in ) = 4.2 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off middle-speed mode, vcc = 5 v, f(x in ) = 4.2 mhz f(x cin ) = stopped output transistors off middle-speed mode, vcc = 5 v, f(x in ) = 4.2 mhz (in wit state) f(x cin ) = stopped output transistors off low-speed mode, vcc = 3 v, f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode, vcc = 3 v, f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off increment when a-d conversion is executed all oscillation stopped (in stp state) output transistors off 400 2
104 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. table 27 a-d converter characteristics (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v, t a = 20 to 85 c, f(x in ) = 250 khz to 4.2 mhz in high-speed mode, unless otherwise noted) note: except ladder resistor for a-d converter table 28 d-a converter characteristics (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v, v ref = 3.0 to vcc, t a = 20 to 85 c, unless otherwise noted) bits % % s k ? ma resolution absolute accuracy (excluding quantization error) setting time output resistor reference power source input current (note) min. 1 ty p. 2.5 max. 8 1.0 2.5 3 4 3.2 unit limits parameter tsu ro i vref test conditions v cc = 4.0 5.5 v v cc = 3.0 5.5 v symbol min. typ. max. symbol parameter limits unit test conditions t conv iv ref i ia r ladder resolution absolute accuracy (excluding quantization error) conversion time reference input current analog port input current ladder resistor v cc = v ref = 5.12 v v ref = 5.0 v 61 50 1 150 0.5 35 10 2.5 62 200 5.0 bits lsb tc( ) a a k ?
105 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. timing requirements table 29 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted) reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width sub-clock input cycle time (x cin input) sub-clock input h pulse width sub-clock input l pulse width cntr 0 cntr 2 input cycle time cntr 0 cntr 2 input h pulse width cntr 0 cntr 2 input l pulse width int 0 int 4 input h pulse width (int 2 when noise filter is not used) (note 1) int 0 int 4 input l pulse width (int 2 when noise filter is not used) (note 1) int 2 input h pulse width (when noise filter is used) (notes 1, 2) int 2 input l pulse width (when noise filter is used) (notes 1, 2) serial i/o1 clock input cycle time serial i/o1 clock input h pulse width serial i/o1 clock input l pulse width serial i/o1 input setup time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 input setup time serial i/o2 input hold time serial i/o3 clock input cycle time serial i/o3 clock input h pulse width serial i/o3 clock input l pulse width serial i/o3 input setup time serial i/o3 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (x cin ) t wh (x cin ) t wl (x cin ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t wh (int 2 ) t wl (int 2 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (s in1 -s clk1 ) t h (s clk1 -s in1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (rxd-s clk2 ) t h (s clk2 -rxd) t c (s clk3 ) t wh (s clk3 ) t wl (s clk3 ) t su (s in3 -s clk3 ) t h (s clk3 -s in3 ) limits s ns ns ns s s s s s s ns ns clks clks ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 2.0 238 60 60 20 5.0 5.0 4.0 1.6 1.6 80 80 3 3 950 400 400 200 200 800 370 370 220 100 1000 400 400 200 200 typ. max. symbol unit notes 1: iidcon2, iidcon3 = 00 when noise filter is not used iidcon2, iidcon3 = 01 or 10 when noise filter is used 2: unit indicates sample clock number of noise filter.
106 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. table 30 switching characteristics (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted) serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o2 output delay time (note 2) serial i/o2 output valid time (note 2) serial i/o3 output delay time (note 3) serial i/o3 output valid time (note 3) serial i/o clock output rising time serial i/o clock output falling time p-channel high-breakdodwn-voltage output rising time (note 4) p-channel high-breakdodwn-voltage output rising time (note 5) t wh (s clk ) t wl (s clk ) t d (s clk1 -s out1 ) t v (s clk1 -s out1 ) t d (s clk2 -txd) t v (s clk2 -txd) t d (s clk3 -s out3 ) t v (s clk3 -s out3 ) t r (s clk ) t f (s clk ) t r (pch strg) t r (pch weak) limits ns ns ns ns ns ns ns ns ns ns ns s parameter min. t c (s clk )/2 160 t c (s clk )/2 160 0 30 0 ty p . 55 1.8 max. 200 140 200 40 40 symbol unit notes 1: when the pb 5 /s out1 p-channel output disable bit of the serial i/o1 control register (bit 7 of address 001a 16 ) is 0 . 2: when the p6 5 /txd p-channel output disable bit of the uart control register (bit 4 of address 0038 16 ) is 0 . 3: when the p9 1 /s out3 p-channel output disable bit of the serial i/o3 control register (bit 7 of address 0eec 16 ) is 0 . 4: when the high-breakdown voltage port drivability selection bit of the fldc mode register (bit 7 of address 0ef4 16 ) is 0 . 5: when the high-breakdown voltage port drivability selection bit of the fldc mode register (bit 7 of address 0ef4 16 ) is 1 . test conditions c l = 100 pf c l = 100 pf c l = 100 pf c l = 100 pf c l = 100 pf v ee = vcc 43 v c l = 100 pf v ee = vcc 43 v fig. 102 circuit for measuring output switching characteristics p 6 6 / s c l k 2 1 , p 6 7 / s c l k 2 2 , p 9 2 / s c l k 3 , p 0 , p 1 , p 2 , p 3 , p 4 , p 5 , p 6 0 p 6 3 p b 4 / s c l k 1 1 p b 0 / s c l k 1 2 , c l c l v e e s e r i a l i / o c l o c k o u t p u t p o r t h i g h - b r e a k d o w n v o l t a g e p - c h a n n e l o p e n - d r a i n o u t p u t p o r t ( n o t e ) n o t e : p o r t s p 4 , p 5 , p 6 0 p 6 3 n e e d e x t e r n a l r e s i s t o r s .
107 38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 103 timing diagram 0.2v cc t wl(x cin ) 0.8v cc t wh(x cin ) t c(x cin ) x cin 0.2v cc t wl(x in ) 0.8v cc t wh(x in ) t c(x in ) x in 0.2v cc 0.8v cc t w(reset) reset 0.2v cc t wl(cntr) 0.8v cc t wh(cntr) t c(cntr) cntr 0 ,cntr 1 0.2v cc t wl(int) 0.8v cc t wh(int) int 0 int 4 0.2v cc t d(s clk -s out ) 0.2v cc 0.8v cc 0.8v cc t r t su(s in -s clk ) t h(s clk -s in ) t v(s clk -s out ) t c(s clk ) t wl(s clk ) t wh(s clk ) s out , txd s in , rxd s clk t f(s clk ) t d(s clk -txd) t v(s clk -txd) t h(s clk -rxd) t su(rxd-s clk )
38b7 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. ? 2000 mitsubishi electric corp. new publication, effective apr. 2000. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product be st suited to the customer s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents info rmation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used unde r circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these ma terials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licens e from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan package outline qfp100-p-1420-0.65 1.58 weight(g) jedec code eiaj package code lead material alloy 42 100p6s-a plastic 100pin 14 ? 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.35 i 2 1.3 m d 14.6 m e 20.6 10 0 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.65 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 0 3.05 e e e e c h e 1 30 31 81 50 80 51 h d d m d m e a f a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100 x 0.13 b x m
rev. rev. no. date 1.0 first edition 10/04/00 revision history 38b7 group data sheet (1/1) revision description

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